Type I PLL Phase Correction for Coherent Frequency Switching
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Solution Overview
Problem
Phase coherence across different frequencies is challenging in phase-locked loops (PLLs), particularly in applications like phase-based distance estimation, where type-II PLLs introduce longer lock times, increased noise, and higher power consumption.
Innovation Solution
The method involves using a type I PLL and applying a correction signal to the feedback path to compensate for phase shifts caused by frequency changes, thereby maintaining phase coherence without the need for a phase error integration block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but lock time increases and power consumption increases
Solution Approach 1:
The patent extracts the phase error integration block from the PLL structure, transitioning from a type-II PLL to a type-I PLL configuration. This removal eliminates the inherent phase lag and longer lock times associated with integration blocks while maintaining phase coherence through alternative compensation mechanisms described in the patent.
Solution Approach 2:
The patent changes the fundamental parameter of PLL type from type-II to type-I, fundamentally altering the loop filter configuration and removing the phase error integration block. This parameter change enables faster lock times and reduced power consumption while maintaining phase coherence through the compensation techniques disclosed.
2Reliability
If type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but power consumption increases
Solution Approach 1:
The patent extracts the phase error integration block from the PLL structure, transitioning from a type-II PLL to a type-I PLL configuration. This removal eliminates the additional power consumption associated with the integration block while maintaining phase coherence through alternative compensation mechanisms described in the patent.
3Reliability
If type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but device complexity increases
Solution Approach 1:
The patent extracts the phase error integration block from the PLL structure, simplifying the overall circuit architecture. This removal reduces device complexity, transistor count, and die area while maintaining phase coherence through the compensation techniques disclosed in the patent.
Data Source
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AI summary
Disclosed herein are methods of using a type I phase locked loop, PLL, comprising an oscillator and a feedback path to a phase detector. The method comprises: locking a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal; locking a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal; and a one of: adjusting the second relative phase to equal the first relative phase, and adjusting the oscillator frequency, by applying a correction to the PLL