U-Shaped Channel Layer Integration for Oxide Semiconductor Optical Performance
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Solution Overview
Problem
The current integration of oxide semiconductor transistors with metal-oxide semiconductor (MOS) transistors falls short in optimizing optical performance due to insufficient fabrication processes.
Innovation Solution
A method involving the formation of a U-shaped channel layer within a semiconductor device, where a substrate with a MOS transistor is surrounded by interlayer dielectric layers, and source and drain layers are formed adjacent to the channel layer, with the top surfaces of all layers being coplanar, enabling efficient integration and fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for integrating oxide semiconductor transistors with MOS transistors, then the integration is achieved, but the optical performance is insufficient
Solution Approach 1:
The fabrication process is divided into distinct stages: forming the U-shaped channel layer structure, creating coplanar source/drain layers, and implementing planarizing processes. This segmentation allows each stage to be optimized independently for both manufacturing ease and optical performance.
Solution Approach 2:
The channel layer is formed in a U-shape configuration before final planarization, and source/drain layers are positioned to achieve coplanarity in advance. This preliminary structuring enables subsequent processes to focus on refinement rather than fundamental formation, improving both manufacturability and optical characteristics.
2Reliability
If the channel layer is formed to improve integration, then the fabrication complexity increases, but the optical performance should improve
Solution Approach 1:
The source layer, drain layer, and channel layer are integrated into a unified coplanar structure. This merging of layers into a single planar configuration reduces fabrication complexity by eliminating the need for separate alignment and positioning processes while maintaining improved optical performance.
Solution Approach 2:
The channel layer transitions from a conventional planar configuration to a U-shaped three-dimensional structure that is then planarized. This dimensional transformation allows the channel to wrap around the gate structure, improving gate control and optical performance while the final planarization maintains manufacturing simplicity.
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.