U-Shaped Channel Memory Floating Gate Notch
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Solution Overview
Problem
U-shaped channel semiconductor memories face challenges in compatibility with logic circuits and chip density due to poor capacitive coupling and increased manufacturing costs and complexity.
Innovation Solution
A notch is formed on the top of the floating gate on one side of the source region, allowing the control gate to cover the floating gate on both sides, enhancing capacitive coupling without increasing the floating gate thickness, and reducing the size of the semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate is extended to cover both sides of the U-shaped groove to improve capacitive coupling, then the capacitive coupling ratio is improved, but the size of the semiconductor memory is increased and chip density is reduced
Solution Approach 1:
The patent introduces a vertical dimension by forming the control gate on the side wall of the floating gate within the U-shaped groove. This three-dimensional configuration allows the control gate to overlap with the floating gate in the vertical direction, providing effective capacitive coupling without requiring horizontal extension of the floating gate, thus maintaining compact chip area while achieving reliable capacitive coupling.
2Reliability
If the thickness of the floating gate is increased to enlarge the contact area with the control gate, then the capacitive coupling ratio is improved, but the manufacturing cost and process difficulty are increased
Solution Approach 1:
Instead of increasing floating gate thickness, the patent utilizes the vertical space within the U-shaped groove to position the control gate on the side wall. This approach achieves enhanced capacitive coupling through vertical overlap rather than increasing material thickness, avoiding additional manufacturing steps and costs associated with thicker floating gate formation.
Solution Approach 2:
The patent concentrates the capacitive coupling function at a specific location - the side wall interface between the control gate and floating gate within the U-shaped groove. This localized configuration provides effective coupling without requiring uniform increases in floating gate dimensions throughout the structure, thereby simplifying manufacturing while maintaining performance.
3Productivity
If the U-shaped channel structure is used to increase the length of current channel region, then the integration density is improved, but the compatibility with logic circuits is poor
Solution Approach 1:
The patent designs the U-shaped channel structure with a planar top surface that can accommodate standard logic circuit fabrication processes. The control gate is formed on the side wall of the floating gate, creating a configuration that serves multiple functions: maintaining high integration density through the U-shaped channel while providing a planar interface compatible with conventional logic circuit manufacturing, thus achieving both high density and broad compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves chip density and reduces manufacturing complexity and costs while maintaining effective capacitive coupling, addressing the limitations of prior U-shaped channel semiconductor memories.
Implementation Method 1
the capacitive coupling effect of the control gate applied on the floating gate
Data Source
AI summary
A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a first layer of insulation film arranged on the U-shaped channel region, a floating gate provided with a notch, a second layer of insulation film, a control gate, a p-n junction diode arranged between the floating gate and the drain region, and a gate controlled diode formed by the control gate, the second layer of insulation film, and the p-n junction diode and using the control gate as a gate. Under the precondition of not increasing the manufacturing cost and difficulty of the semiconductor memory with a U-shaped channel and not affecting the performance of the semiconductor memory with a U-shaped channel, the dimension of a semiconductor storage device is further reduced and the chip density is increased by arranging the notch in the floating gate.