U-Shaped Common Line Structure for TFT Aperture Ratio

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Solution Overview

Problem

Conventional thin film transistor array substrates suffer from aperture ratio loss due to overlapping common lines with pixel electrodes, and reducing line width or changing line shape can lead to increased resistance and defects like line cut or shutdown crosstalk.

Innovation Solution

A thin film transistor array substrate with a 'U'-shaped common line structure, where the line width is increased from the region near the thin film transistor to below the drain electrode, minimizing overlap with the pixel electrode and preventing line cut by maintaining a wider channel region, thereby reducing resistance and maintaining aperture ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the common line is formed to overlap the pixel electrode to define a storage capacitor, then the storage capacitor is formed, but the aperture ratio is reduced due to the overlap area

Engineering Contradiction:
Improvestorage capacitor formationVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The common line is extended into the third dimension by passing below the drain electrode through a contact hole. This vertical arrangement allows the common line to overlap the pixel electrode in the vertical direction without occupying horizontal aperture area, thus forming the storage capacitor while maintaining the aperture ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the line width of the common line is reduced or the line shape is changed to prevent aperture ratio loss, then the aperture ratio is improved, but the resistance increases and defects like line cut occur

Engineering Contradiction:
Improveaperture ratioVSAvoidline resistance and defects
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The common line is configured with different line widths in different regions: a first line width in the region overlapping the pixel electrode (where aperture ratio matters), and a second, larger line width in the region below the drain electrode (where electrical connection matters). This local differentiation allows the line to maintain low resistance where needed while minimizing aperture ratio loss where it overlaps the pixel electrode.

Inventive Principle:
Principle #3Local quality

3Reliability

If the common line passes below the drain electrode with increased line width, then the resistance is decreased, but the device complexity increases

Engineering Contradiction:
Improveline resistanceVSAvoidcommon line structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The common line is segmented into distinct functional regions: a first pattern region overlapping the pixel electrode, a second pattern region adjacent to data lines, and a third pattern region below the drain electrode. Each segment serves a specific function, allowing the overall structure to achieve low resistance and proper capacitor formation while maintaining manufacturability through clear regional differentiation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8304768B2Thin film transistor array substrate and method for manufacturing the same
Publication Date: 2012.11.06 LG DISPLAY CO LTD
  • US8304768B2 patent drawing
  • US8304768B2 patent drawing
  • US8304768B2 patent drawing

AI summary

A thin film transistor array substrate includes according to an embodiment a plurality of gate lines and a plurality of data lines on a substrate, to define pixel regions crossing each other; thin film transistors each formed at the intersection of the gate lines and the data lines, and including a gate electrode, a source electrode and a drain electrode; common lines, each including a first pattern formed across the data lines, a second pattern formed adjacent to the data lines on both sides in the pixel region and parallel to the data lines, and a third pattern formed adjacent to the gate lines to connect the second pattern disposed on both the sides in the associated one of the pixel regions, and passing below the drain electrode of the thin film transistors; and pixel electrodes formed in the pixel regions.