U-Shaped Contact Structure for Reliable 3D Memory Stacks

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Solution Overview

Problem

The integration of semiconductor devices is limited by the area occupied by unit memory cells, and there is a need for improved operational reliability in three-dimensional semiconductor devices with stacked memory cells.

Innovation Solution

A semiconductor device with a contact structure having a U-shape, including contact vias and plugs, and a manufacturing method involving the formation of trenches, contact holes, and via holes, followed by expansion and formation of contact structures to enhance electrical connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional semiconductor devices with stacked memory cells are used to improve integration density, then the degree of integration is improved, but operational reliability deteriorates

Engineering Contradiction:
Improvedegree of integrationVSAvoidoperational reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure is segmented into multiple components: contact vias extending through the stack, a U-shaped contact connection portion, and contact plugs. This segmentation allows each component to perform its specific function optimally, improving both integration density and operational reliability through distributed contact points rather than a single contact structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact connection portion extends in a first direction (horizontal/planar direction) to connect contact vias that are spaced apart, adding a dimensional aspect to the contact structure. This planar extension within the U-shape configuration enables reliable electrical connection across the stacked memory cells while maintaining compact vertical integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional contact structures are used in stacked memory cells, then manufacturing is simpler, but electrical connectivity and reliability deteriorate

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidelectrical connectivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The contact vias are formed extending through the stack before the contact connection portion is created. This preliminary formation of vertical contact pathways through the stacked memory cells allows subsequent planar connection to be established more easily, improving electrical connectivity while maintaining a systematic manufacturing approach.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The contact structure merges vertical contact vias with a horizontal contact connection portion in a unified U-shaped configuration. This combination integrates both the through-stack connection function and the planar interconnection function into a single structure, improving electrical connectivity without requiring separate manufacturing processes for each function.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If contact vias are spaced apart in the contact structure, then signal transmission is improved, but structural complexity increases

Engineering Contradiction:
Improvesignal transmissionVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact connection portion has an asymmetric U-shape configuration with specific spacing between contact vias. This asymmetric design optimizes signal transmission by providing appropriate spacing to reduce interference while maintaining compact overall structure. The U-shape itself is asymmetric, with the opening facing a specific direction to accommodate the spacing requirements for improved signal transmission.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250266351A1Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2025.08.21 SK HYNIX INC
  • US20250266351A1 patent drawing
  • US20250266351A1 patent drawing
  • US20250266351A1 patent drawing

AI summary

A semiconductor device includes: a peripheral circuit, a stack located over the peripheral circuit, a bonding pad located between the peripheral circuit and the stack, a probing pad located between the peripheral circuit and the stack and connected to the bonding pad, a contact plug extending through the stack and electrically connected to the peripheral circuit through the probing pad and the bonding pad, and a contact structure including a contact connect portion extending in a first direction, a first contact via protruding from the contact connect portion in a second direction intersecting the first direction, and a second contact via spaced apart from the first contact via and protruding from the contact connection portion in the second direction.