U-Shaped Charge Storage Layer in 1.5 Transistor Flash Memory
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Solution Overview
Problem
The manufacturing process of conventional SONOS flash memory with 1.5 transistors per cell is complex due to the formation of the control gate, which influences peripheral memory cell control circuit transistors and increases the risk of short circuits between the control and select gates, leading to over-erase issues and high costs.
Innovation Solution
A modified fabrication process where a U-shaped groove is formed on a P-well with sacrifice films, allowing for self-aligned formation of the control and select gates, reducing the complexity and risk of short circuits by using a metallic control gate covered with an insulating film before forming the select gate, and optimizing the etching depth to simplify the optimization of programming, erasing, and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SONOS flash memory manufacturing process is used with control gate formation, then charge storage capability is achieved, but the manufacturing process becomes complex and the risk of short circuits between control and select gates increases
Solution Approach 1:
An insulating film is formed on the control gate before the select gate is created. This preliminary insulation layer prevents direct contact between the control gate and select gate, eliminating the short circuit risk while simplifying the manufacturing process by avoiding complex alignment requirements
Solution Approach 2:
An insulating film is introduced as an intermediary layer between the control gate and select gate. This intermediate layer acts as a physical barrier that prevents short circuits while allowing both gates to function independently, thereby reducing manufacturing complexity and improving reliability
2Reliability
If control gate is formed later in the process, then charge storage function is achieved, but peripheral memory cell control circuit transistors are influenced and over-erase occurs
Solution Approach 1:
The insulating film serves as a mediator that isolates the control gate from the select gate and peripheral transistors. This isolation prevents the control gate formation process from adversely affecting peripheral memory cell control circuit transistors, eliminating the over-erase effect and expanding the operation margin
3Area of moving object
If 1.5 transistors per cell structure is used, then cell area is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The insulating film is formed on the control gate in advance, before select gate formation. This preliminary action simplifies the subsequent manufacturing steps by eliminating the need for complex alignment processes, thereby reducing manufacturing complexity and cost while maintaining the compact 1.5 transistor per cell structure
Solution Approach 2:
The insulating film formation process serves multiple functions: it provides electrical isolation, defines gate boundaries, and simplifies subsequent processing. This self-service approach reduces the need for additional manufacturing steps, making the production of compact 1.5 transistor cells more economical
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces the influence on peripheral transistors, prevents short circuits, and enhances the operational margin by allowing for a more efficient and cost-effective production of flash memory with improved read speed and reduced cell area.
Implementation Method 1
using a metallic control gate covered with an insulating film before forming the select gate, and optimizing the etching depth to simplify the optimization of programming, erasing, and reading
Data Source
AI summary
A cheap and high performance 1.5 transistor-type flash memory highly compatible externally of a memory region has a sacrifice film formed on a substrate. A U-shaped groove is formed on the sacrifice film, where multiple insulating films are laminated. The multiple insulating films includes a silicon nitride film as a charge storage layer. Low resistive material is disposed on the multiple insulating films to form a control gate. The select gate is formed on the insulating film on a side of the control gate in a self-aligned manner. Semiconductor regions opposite in conductivity to the substrate on both sides of the adjoining control gate and the select gate form a source and a drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with the adjoining control gate and the select gate between the source and the drain. In a MOS-type transistor with the control gate, the threshold voltage is changeable according to injection/emission of the charge to the silicon nitride as the charge storage layer, and thus work as a non-volatile memory.