U-Shaped Floating Gate Memory Structure for Flash Scaling
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Solution Overview
Problem
The scaling down of flash memory cells to achieve higher device density results in a shortened floating gate channel, decreased performance, and process control issues due to the influence of the pocket doping region by the source/drain doping region.
Innovation Solution
A two-bit memory structure with U-shaped floating gates and a local doping region replaces the conventional pocket doping region, extending the floating gate channel and improving process control, while increasing the gate-induced leakage effect for enhanced programming and reading speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the floating gate channel is shortened to scale down flash memory cells for higher device density, then device density is improved, but performance deteriorates
Solution Approach 1:
The floating gate structure transitions from a conventional planar configuration to a U-shaped configuration that extends into the substrate vertically. This dimensional change allows the floating gate channel to maintain sufficient length for good performance while the overall device footprint is reduced, achieving higher device density without sacrificing performance.
Solution Approach 2:
The U-shaped floating gate is embedded within the substrate, with the floating gate channel wrapping around the U-shaped bottom. This nested configuration allows the floating gate channel to be extended into the substrate volume, effectively increasing the functional channel length without increasing the planar device area.
2Ease of manufacture
If the pocket doping region is positioned adjacent to the source/drain doping region to follow conventional fabrication, then fabrication process is simplified, but process control deteriorates due to influence between regions
Solution Approach 1:
The pocket doping region is extracted from its conventional position adjacent to the source/drain doping region and relocated to position directly below the floating gate. This separation removes the harmful influence between the pocket doping region and source/drain doping region, improving process control while maintaining ease of fabrication through standard doping processes.
3Volume of moving object
If conventional floating gate structures are used with scaled dimensions, then device size is reduced, but the process window deteriorates
Solution Approach 1:
By extending the floating gate channel into the substrate through the U-shaped configuration, the effective channel length is maintained even as the device footprint is reduced. This provides process robustness and a larger process window while achieving scaled dimensions.
Solution Approach 2:
The U-shaped bottom portion of the floating gate is positioned locally below the floating gate channel, creating a localized extension that enhances the channel length specifically where needed. This local structural modification improves process window without requiring changes to the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The U-shaped floating gates and local doping region configuration maintain performance and increase the process window, improving the flash memory's programming and reading speed, and providing better control over the fabrication process.
Implementation Method 1
the memory structure provided in the invention can increase the gate induced leakage (GIDL) effect. In this way, the programming and reading speed of the flash memory is increased
Data Source
AI summary
A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.