U-Shaped Floating Gate for Flash Memory Integration
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Solution Overview
Problem
The existing manufacturing processes for flash floating poly gate structures in semiconductor devices result in reduced surface area and coupling ratio, leading to yield and reliability issues in flash memory devices.
Innovation Solution
The use of a meta-stable poly silicon (MPS) process to form a crown-shaped floating gate and poly particle-shaped MPS, combined with an oxide-nitride-oxide dielectric layer and control gate, increases the surface area and coupling ratio of the capacitor in flash memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high integration is obtained by using conventional flash floating poly gate manufacturing processes, then the area occupied by capacitor is reduced, but the surface area of capacitor and coupling ratio are significantly reduced leading to deteriorated yield and reliability
Solution Approach 1:
The floating gate is segmented into a conventional planar portion and a U-shaped portion that extends into the substrate. This segmentation allows the capacitor to have both a reduced planar area (improving integration) and an increased effective surface area through the U-shaped structure (maintaining coupling ratio and reliability).
Solution Approach 2:
The invention transitions from a two-dimensional planar capacitor structure to a three-dimensional structure by forming a U-shaped floating gate that extends vertically and laterally into the substrate. This dimensional change increases the effective surface area of the capacitor without increasing the planar footprint, thus maintaining coupling ratio while achieving high integration.
2Productivity
If high integration is obtained by using conventional flash floating poly gate manufacturing processes, then the area occupied by capacitor is reduced, but the coupling ratio is significantly reduced
Solution Approach 1:
The floating gate is divided into planar and U-shaped segments, where the U-shaped segment provides additional capacitance surface area. This segmentation enables the capacitor to maintain a high coupling ratio despite reduced planar area, as the U-shaped portion contributes additional effective surface area for charge storage.
Solution Approach 2:
By extending the floating gate into the substrate in a U-shape configuration, the invention adds a vertical dimension to the capacitor structure. This increases the effective surface area available for coupling without increasing the planar area occupied, thereby maintaining coupling ratio while achieving high integration density.
3Ease of manufacture
If conventional manufacturing processes are used, then manufacturing is simpler, but the surface area of capacitor is reduced leading to deteriorated performance
Solution Approach 1:
The U-shaped floating gate structure is formed during the standard fabrication sequence by incorporating additional patterning and etching steps at appropriate stages. The meta-stable polysilicon layer is deposited and processed along with the conventional floating gate formation, integrating the enhanced structure into the existing manufacturing flow without requiring a complete process overhaul.
Solution Approach 2:
The invention introduces meta-stable polysilicon (MPS) as a new material parameter in the floating gate structure. MPS has unique properties that allow it to be deposited at lower temperatures and processed differently from conventional polysilicon, enabling the formation of the U-shaped structure with standard equipment while achieving the desired performance enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield and reliability of semiconductor devices by maintaining high integration, reducing manufacturing costs, and maximizing performance while preventing a reduction in capacitor area and coupling ratio.
Implementation Method 1
poly particle-shaped MPS 413 can be formed by performing an MPS annealing process in an N2 atmosphere at a reaction temperature between 800° C. and 1,500° C.
Implementation Method 2
performing an MPS annealing process in an N2 atmosphere at a reaction temperature between 800° C. and 1,500° C.
Implementation Method 3
A dielectric layer can be composed as oxide-nitride-oxide (ONO) layer 415
Data Source
AI summary
A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.