U-Shaped Floating Gate for High-Density Nonvolatile Memory
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Solution Overview
Problem
High integration density in nonvolatile memory devices leads to decreased distance between wordlines, making it difficult to achieve a sufficient coupling ratio between control and floating gate electrodes, resulting in electrical interference and data variability, and existing methods to increase coupling ratio, such as modifying the sectional shape of the floating gate electrode, cause technical issues like electrical defects and parasitic transistors.
Innovation Solution
A method of fabricating nonvolatile memory devices involving the formation of trench mask patterns on a semiconductor substrate, creating substrate trenches, and forming device isolation layer patterns, with specific conductive patterns and sacrificial layers to achieve a 'U' or 'inverted T' shaped floating gate electrode structure that reduces electrical interference while maintaining a high coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between wordlines is decreased to increase integration density, then the integration density is improved, but the coupling ratio between control and floating gate electrodes deteriorates
Solution Approach 1:
The patent introduces a third dimension by forming the floating gate electrode with a U-shaped or inverted T-shaped cross-section, extending vertically between wordlines. This dimensional change allows the floating gate to maintain sufficient coupling area with the control gate despite reduced horizontal spacing between wordlines, thus resolving the contradiction between integration density and coupling ratio.
Solution Approach 2:
The floating gate electrode is nested between adjacent wordlines (control gates), with the U-shaped or inverted T-shaped structure fitting within the vertical space between them. This nesting arrangement maximizes the use of available space while maintaining electrical coupling, enabling high integration density without sacrificing coupling ratio.
2Reliability
If the facing area between control and floating gate electrodes is increased to improve coupling ratio, then the coupling ratio is improved, but electrical interference between adjacent wordlines worsens
Solution Approach 1:
The patent applies local quality by giving different regions of the floating gate electrode different functions: the horizontal bottom portion provides coupling area with the control gate, while the vertical extended portions are positioned to avoid interference with adjacent wordlines. This localized functional differentiation allows the floating gate to achieve sufficient coupling ratio without generating harmful electrical interference.
Solution Approach 2:
The U-shaped or inverted T-shaped cross-section of the floating gate electrode represents an asymmetric structure that optimizes the distribution of coupling area. The asymmetric shape concentrates the coupling function at the bottom portion while limiting the lateral extent of the structure, thereby maintaining coupling ratio without increasing interference with neighboring wordlines.
3Reliability
If the height of the floating gate electrode is increased to improve coupling ratio, then the coupling ratio is improved, but the formation of parasitic transistors worsens
Solution Approach 1:
The patent applies local quality by differentiating the function of different parts of the floating gate structure. The vertical extended portions are localized at the sides of the active region and are designed to terminate before reaching the level that would cause parasitic transistor formation. This localized design allows the floating gate to achieve sufficient height for coupling while avoiding the harmful effect of parasitic transistors.
Data Source
AI summary
Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening. The extended portion has a smaller width than the bottom portion. A second lower conductive pattern is formed filling the second opening.