U-Shaped Gate MOS Transistor for Leakage Control
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Solution Overview
Problem
MOS transistors face challenges in minimizing leakage currents and increasing integration density while maintaining performance, particularly as they miniaturize, with existing techniques being complex and introducing stray capacitances that decrease switching speed.
Innovation Solution
A MOS transistor design featuring a U-shaped channel-forming semiconductor region with source and drain regions of the same U shape, coated with a conductive gate and insulating material, formed in an active area of a semiconductor substrate with insulating trenches, using a material of low dielectric permittivity for the insulating surfaces, and a manufacturing method that includes doping and sacrificial material processing to enhance electrostatic control and reduce stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS transistors are miniaturized to increase integration density, then integration density is improved, but leakage currents increase
Solution Approach 1:
The patent transitions from conventional planar transistor geometry to a three-dimensional structure where the gate wraps around the channel in a U-shaped configuration. This dimensional change allows the gate to control the channel from multiple directions, providing superior electrostatic control that suppresses leakage currents even as the transistor size is reduced for higher integration density.
Solution Approach 2:
The patent employs a gate structure composed of multiple materials with different dielectric permittivities. The gate insulator includes a first insulating layer with higher dielectric permittivity and a second insulating layer with lower dielectric permittivity. This composite structure optimizes the electrostatic control over the channel while managing leakage currents, allowing the transistor to maintain performance at scaled dimensions.
2Productivity
If gate length is decreased to improve integration density, then integration density is improved, but leakage currents increase due to new effects
Solution Approach 1:
By wrapping the gate around the channel in a U-shaped configuration, the patent extends gate control into the vertical and lateral dimensions rather than relying solely on horizontal gate length. This allows effective channel control even when the gate length is reduced, suppressing short-channel effects and leakage currents at scaled dimensions.
Solution Approach 2:
The patent modifies the gate structure geometry by introducing a U-shaped configuration that wraps around the channel. This geometric parameter change increases the effective gate control area and improves electrostatic control over the channel, counteracting the increased leakage currents that occur when gate length is decreased for higher integration density.
3Reliability
If fin structures are used to improve electrostatic control, then electrostatic control is improved, but stray capacitances increase
Solution Approach 1:
The patent adopts a U-shaped gate structure that wraps around the channel, providing electrostatic control from multiple directions rather than relying on vertical fin structures. This dimensional approach improves electrostatic control while minimizing the exposure of channel surfaces to surrounding structures, thereby reducing stray capacitances.
Solution Approach 2:
Instead of using fin structures that extend vertically into the substrate and create large surface areas prone to stray capacitance, the patent inverts the approach by wrapping the gate around a planar or lightly-raised channel. This inversion provides strong electrostatic control through the wrapped configuration while minimizing the channel surface area exposed to parasitic capacitance sources.
4Object-generated harmful factors
If doping levels are adapted to attenuate leakage effects, then leakage currents are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent addresses leakage current suppression through a geometric solution—the U-shaped gate wrapping around the channel—rather than relying solely on complex doping profiles. This structural approach provides effective electrostatic control to suppress leakage while avoiding the manufacturing complexity associated with multi-layer doping schemes.
Solution Approach 2:
The patent modifies the gate structure geometry to a U-shaped configuration that wraps around the channel, changing the spatial distribution of the gate field. This parameter change in gate geometry provides effective leakage suppression through improved electrostatic control without requiring complex doping level adaptations, thereby reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases effective gate width, decreases stray capacitances, and simplifies interconnect formation, leading to improved performance and ease of integration in circuits like SRAMs, with reduced leakage currents and enhanced switching speed.
Implementation Method 1
MOS transistors formed in SOI-type silicon on-insulator layers sufficiently thin for the gate to act across the entire silicon layer thickness when it is activated
Implementation Method 2
the insulating material covering the internal surfaces of the source and drain regions comprises a material of low dielectric permittivity
Data Source
AI summary
A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.