U-Shaped High-K Charge Storage Layer for Gate Last Nonvolatile Memory
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Solution Overview
Problem
Conventional e-fuse memory devices are incompatible with gate last processes, requiring a new nonvolatile memory device integration to replace them, and existing methods fail to effectively reduce electrical resistance and device size.
Innovation Solution
A nonvolatile memory device with a first stacked gate structure comprising a tunneling dielectric layer, charge storage layer, inter-gate dielectric layer, and a first metal gate, where the first metal gate serves as a controlling gate, and a manufacturing method involving the formation of these layers to reduce electrical resistance and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gate last process is performed on the wafer, then the manufacturing process compatibility is improved, but the original polysilicon layer is removed and cannot provide the required function for conventional e-fuse memory devices
Solution Approach 1:
The patent changes the material parameter of the gate structure from conventional polysilicon to a stacked structure comprising a high-K charge storage layer (such as silicon nitride or silicon oxynitride) and a metal gate layer. This material parameter change enables the device to maintain functionality under gate last process conditions while achieving lower electrical resistance and better compatibility with the manufacturing process.
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple layers: a tunneling dielectric layer, a high-K charge storage layer, an inter-gate dielectric layer, and a metal gate layer. This composite structure combines the advantages of different materials to achieve both process compatibility and functional reliability, replacing the single-material polysilicon gate.
2Volume of moving object
If the electrical resistance of the memory device is reduced, then the device size can be further reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar gate structure to a vertically stacked three-dimensional gate structure. By adding the vertical dimension with multiple thin layers (tunneling dielectric, charge storage layer, inter-gate dielectric, and metal gate), the device achieves reduced footprint area while managing the complexity through standardized layer deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces electrical resistance and device size, enabling the nonvolatile memory device to operate with lower voltage and higher electrical field, while integrating the gate last and high-K last processes to save manufacturing costs.
Implementation Method 1
a tunneling dielectric layer, a charge storage layer
Implementation Method 2
a nonvolatile memory device by integrating a gate last process and a high-K last process
Data Source
AI summary
A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.