U-Shaped Inner Spacer Structures for Nano-Sheet Gate Control
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Solution Overview
Problem
The challenge in nano-sheet-based devices is the reliable fabrication of inner spacer structures, which degrades device performance and increases processing complexity as these devices continue to scale down, making it difficult to maintain effective gate control and mitigate short-channel effects.
Innovation Solution
A method for fabricating nano-sheet-based devices involves forming U-shaped inner spacers and air spacers between the semiconductor layers and the gate structure, using a spacer layer with specific etching processes to create gaps that allow for reliable separation of source/drain features from the metal gates, thereby improving device performance and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for inner spacer structures, then manufacturing process is simpler, but device performance degrades and reliability decreases due to inability to maintain effective gate control and mitigate short-channel effects
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming mandrels, depositing first spacers, forming gaps, depositing second spacers, and selective removal. This segmentation allows each step to be optimized independently, achieving reliable inner spacer formation while managing overall process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
Mandrels are formed in advance before the actual spacer structures are created. These preliminary mandrel structures serve as templates that guide subsequent spacer deposition and define the final inner spacer geometry, ensuring precise positioning and reliable formation without requiring complex direct patterning methods.
2Productivity
If device dimensions are reduced to continue scaling, then production efficiency improves and costs decrease, but fabrication reliability of inner spacer structures deteriorates and processing complexity increases
Solution Approach 1:
The patent introduces intermediate structures (mandrels, first spacers, gap regions) that mediate the formation of final inner spacers. These intermediary elements enable precise control at reduced dimensions by providing physical templates and separation zones, allowing reliable inner spacer fabrication even as device features scale down to smaller dimensions.
Solution Approach 2:
The fabrication process utilizes vertical dimensionality through stacked layers (mandrels, spacers, gaps arranged in multiple levels) to achieve precise lateral positioning of inner spacers. This dimensional approach allows control of sub-10nm features through thicker, more controllable deposition layers, maintaining fabrication reliability during scaling.
3Device complexity
If inner spacer structures are not properly formed, then processing is simpler, but gate control is compromised and short-channel effects increase
Solution Approach 1:
The patent creates different spacer structures at different locations: outer spacers formed on gate sidewalls and inner spacers formed within gaps between channel regions. Each location receives a customized spacer structure optimized for its specific function, enabling precise control of gate-to-source/drain spacing and achieving the required manufacturing precision for effective gate control.
Solution Approach 2:
The spacer system is segmented into multiple components (outer spacers, inner spacers, mandrels) that can be independently formed and controlled. This segmentation allows precise adjustment of each spacer's dimensions and positioning to achieve optimal gate control, with outer spacers defining gate extent and inner spacers providing additional separation, thereby achieving high manufacturing precision.
Data Source
AI summary
A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source drain feature.