U-Shaped Inner Spacer Structures for Nano-Sheet Gate Separation

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Solution Overview

Problem

Challenges in reliably fabricating inner spacer structures for nano-sheet-based devices have arisen, degrading device performance and increasing processing complexity, as existing methods are inadequate for reliably separating the gate structure from source/drain features.

Innovation Solution

A method for forming inner spacers in nano-sheet-based devices involves creating gaps between semiconductor layers, depositing a spacer layer, and selectively etching it to form U-shaped inner spacers that reliably separate epitaxial source/drain features from metal gates, using controlled etching processes to maintain a specific profile and dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication methods are used for inner spacer structures, then processing complexity increases and reliability decreases, but device scaling continues

Engineering Contradiction:
Improveinner spacer fabrication reliabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming gaps between semiconductor layers before depositing the spacer material. This preliminary gap formation enables subsequent conformal spacer deposition to reliably separate gate and source/drain features, resolving the fabrication reliability issue while maintaining processing efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct sequential steps: gap formation, spacer material deposition, and selective etching. This segmentation allows each step to be optimized independently, improving inner spacer reliability without proportionally increasing overall processing complexity

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If inner spacer structures are not reliably fabricated, then device performance degrades, but fabrication methods remain unchanged

Engineering Contradiction:
Improveinner spacer separation precisionVSAvoiddevice performance reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Gaps are formed between semiconductor layers as a preliminary step before spacer deposition. This ensures precise positioning and separation of future source/drain features from gate structures, directly improving manufacturing precision and device performance reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer material is selectively deposited and etched to create U-shaped inner spacers with specific local geometry. This local quality control ensures precise separation at critical interfaces between gate and source/drain regions, enhancing manufacturing precision

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances device performance by ensuring reliable separation of source/drain features, improving fabrication efficiency and reducing complexity, while maintaining gate control and mitigating short-channel effects.

Implementation Method 1

selectively etching it to form U-shaped inner spacers that reliably separate epitaxial source/drain features from metal gates

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

depositing a spacer layer

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS12588247B2Spacer structures for nano-sheet-based devices
Publication Date: 2026.03.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12588247B2 patent drawing
  • US12588247B2 patent drawing
  • US12588247B2 patent drawing

AI summary

A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source/drain feature.