U-Shaped Memory Strings for Low Resistance Word Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional semiconductor storage devices face challenges in reducing wiring resistance of word lines and require complex thermal processes to prevent impurity diffusion, which increases costs and complicates device operation.
Innovation Solution
A non-volatile semiconductor storage device with memory strings featuring a W-shaped semiconductor layer, plate-like word lines, and a back-gate line configuration that reduces wiring resistance and simplifies manufacturing by eliminating the need for source-line wiring, using a laminated structure with tunnel and block insulation films for electric charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source lines are highly doped with impurities to lower resistance, then contact resistance with source lines is improved, but thermal diffusion of impurities occurs requiring complex thermal process control
Solution Approach 1:
The invention extracts the source line function from the conventional three-dimensional memory structure by forming source lines on the same surface as bit lines through U-shaped memory string configuration. This eliminates the need for deep trench contacts to the bottom surface, thereby removing the complex thermal diffusion control requirements while maintaining low contact resistance through surface-level highly doped regions.
Solution Approach 2:
Instead of forming source lines on the bottom surface as in conventional designs, the invention inverts the approach by configuring memory strings in U-shape to enable source line formation on the top surface alongside bit lines. This inversion eliminates the need for through-substrate contacts and associated thermal management complexity.
2Productivity
If word lines are formed separately for each memory string to enable three-dimensional arrangement, then memory integration is improved, but wiring resistance of word lines increases
Solution Approach 1:
The invention merges multiple word lines into a single shared word line that serves multiple U-shaped memory strings simultaneously. This consolidation reduces the total number of word lines required, thereby lowering overall wiring resistance while maintaining three-dimensional memory integration through the shared word line architecture that controls multiple memory strings.
Solution Approach 2:
A single word line is designed to serve multiple memory strings universally, performing the same selection function for different U-shaped memory string configurations. This multi-functional approach reduces wiring complexity and resistance while achieving high memory integration through efficient resource sharing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high integration and reduced manufacturing costs by lowering wiring resistance and simplifying the design and manufacturing process, while maintaining reliable conducting properties and data retention.
Implementation Method 1
an electric charge storage layer formed to surround side surfaces of the columnar portions
Implementation Method 2
a gate insulation film, with the first direction taken as a longitudinal direction, the second conductive layer functioning as control electrodes of the selection transistors
Data Source
AI summary
A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.