U-Shaped Metal Gate Structure Reducing RC Delay
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Solution Overview
Problem
Conventional metal gate electrodes in integrated circuits exhibit high gate resistance due to the small area occupancy of lower resistance metal layers, leading to increased RC delay and degraded device performance.
Innovation Solution
A method of forming a gate structure where a trench is created in a dielectric layer, filled with a first metal material for the bottom portion and a second metal material with lower resistance for the top portion, ensuring the second material's maximum width equals the first material's width and extending into recesses, with a co-planar top surface with the gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multilayered metal gate electrode is formed with a lower resistance metal layer, then gate resistance is reduced, but the lower resistance metal layer occupies a small area ratio leading to increased RC delay
Solution Approach 1:
The patent transitions from a conventional planar metal gate structure to a 3D U-shaped metal gate structure that extends into the trench. This dimensional change allows the lower resistance metal layer to occupy a larger effective area by utilizing the vertical depth of the trench, thereby reducing gate resistance without increasing horizontal footprint and avoiding increased RC delay.
Solution Approach 2:
The patent implements a nested multilayered metal gate structure where different metal layers with different resistance characteristics are stacked within the U-shaped trench. The lower resistance metal layer is positioned to maximize its contribution to gate conductivity while maintaining compact integration, effectively nesting functional layers to resolve the resistance-delay tradeoff.
2Reliability
If the thickness of the gate oxide is reduced to maintain performance with decreased gate length, then device performance is maintained, but gate leakage increases
Solution Approach 1:
The patent employs a composite gate dielectric structure combining high-k dielectric material with a thin interfacial oxide layer. The high-k material provides the necessary insulation with greater physical thickness to prevent gate leakage, while the thin interfacial oxide ensures good electrical contact and device performance, effectively resolving the leakage-performance contradiction.
Data Source
AI summary
A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.