U-Shaped NAND Flash Strings With Bottom Gate Control
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices face challenges in efficiently performing erase operations and reducing source line resistance, while also enhancing integration density, particularly in structures like Pipe-shaped BiCS and TCAT, where conventional erase methods are inefficient and source line resistance is high.
Innovation Solution
A nonvolatile memory device with vertically stacked memory cells, featuring active regions with P-type semiconductors, first and second vertical strings, and select transistors, where a bottom gate or word line controls the connection between these strings, allowing for efficient erase operations and reduced source line resistance by applying specific voltages to form inverted regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If channels are separated from the substrate body in Pipe-shaped BiCS structure, then degree of integration is improved and source line resistance is reduced, but erase operation efficiency deteriorates
Solution Approach 1:
The memory device is divided into multiple stacked layers with channels separated from the substrate body, forming independent vertical string structures. This segmentation allows for improved integration density while maintaining erase capability through alternative mechanisms such as selection gate-induced GIDL current that does not require direct substrate contact.
Solution Approach 2:
Selection gates are introduced as intermediary elements that enable erase operations without direct substrate contact. The selection gates generate GIDL current that serves as the mediator to inject holes into channels for data erasure, replacing the conventional substrate-based F-N tunneling mechanism.
2Device complexity
If source lines are formed in substrate by ion implantation through narrow slits in TCAT structure, then degree of integration is improved, but source line resistance markedly increases
Solution Approach 1:
The source lines are repositioned from the substrate plane to the upper surface, forming source line contacts that extend vertically to contact the channels. This dimensional change allows for wider, lower-resistance source line paths while maintaining the integrated vertical structure of the memory device.
Solution Approach 2:
Multiple source line contacts are created that replicate the channel connections at the upper surface level. These copied connection paths provide redundant, low-resistance routes for current flow, reducing overall source line resistance while maintaining integration density.
3Device complexity
If both bit lines and source lines are located over stacked memory cells in Pipe-shaped BiCS structure, then degree of integration is improved and only one layer of selection gates is needed, but conventional F-N tunneling erase becomes impossible
Solution Approach 1:
The erase mechanism is changed from F-N tunneling (which requires substrate contact) to GIDL current generation (which uses selection gates). This parameter change in the physical mechanism allows the device to maintain the integrated structure with lines over stacked cells while enabling erase operations through a different physical process.
Solution Approach 2:
Instead of using substrate contact to generate erase current (conventional approach), the invention inverts the approach by using selection gate contact to generate erase current through GIDL mechanism. This inversion enables erase operations in the new structural configuration where substrate contact is not available.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables efficient erase operations and reduces source line resistance, improving integration density by allowing for low-resistance metal implementation of bit and source lines, while maintaining operational efficiency similar to conventional structures.
Implementation Method 1
a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string
Implementation Method 2
data are erased in such a way as to inject holes, which are produced by GIDL (gate induced drain leakage) current flown when a high voltage is applied to selection gates, into channels
Data Source
AI summary
A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.