3D U-Shaped Nanosheet CFET Layout for Higher Transistor Density
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors beyond single-digit nanometer nodes, particularly in creating three-dimensional (3D) logic chip designs, as traditional two-dimensional (2D) circuits struggle to increase transistor density effectively.
Innovation Solution
A method for manufacturing semiconductor devices with a complex channel structure featuring a main portion and tail portions, where source-drain (S-D) ends are offset from the main portion, and a gate all around (GAA) structure is formed around the main portion, allowing for the vertical stacking of transistors with S-D contacts that are epitaxially grown or formed using silicide, enabling efficient 3D integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional circuit fabrication is used, then manufacturing process simplicity is maintained, but transistor density cannot be effectively increased beyond single-digit nanometer nodes
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistor layouts to three-dimensional vertically stacked transistor structures. Multiple transistor layers are stacked above the substrate, with each layer containing transistors that can be controlled by gate electrodes. This dimensional change allows transistor density to increase from area-based to volume-based scaling, enabling effective density improvement at single-digit nanometer nodes while managing fabrication complexity through systematic process integration.
2Quantity of substance
If three-dimensional transistor stacking is implemented, then transistor density is increased, but fabrication process complexity increases significantly
Solution Approach 1:
The fabrication process is divided into distinct segments: forming insulating layers with patterns of openings, selectively forming semiconductor layers in specific regions, and sequentially creating gate electrodes and source/drain electrodes in different stages. This segmentation allows complex 3D transistor structures to be built through manageable, repeatable process modules that can be executed using existing semiconductor fabrication equipment and techniques.
Solution Approach 2:
Insulating layers and their patterned openings are formed in advance before semiconductor layers and transistor structures are created. These pre-formed insulating structures serve as templates and isolation elements that guide subsequent fabrication steps, enabling precise positioning of transistors and gates while simplifying later processing stages.
3Area of stationary object
If vertical stacking of transistors is performed, then area utilization is improved, but source-drain contact formation becomes more difficult
Solution Approach 1:
Source/drain electrodes are formed with different configurations in different vertical layers. In first transistor layers, source/drain electrodes extend in first directions, while in second transistor layers, they extend in second directions. This local differentiation allows optimized contact formation for each layer's specific requirements while maintaining overall 3D integration, reducing the complexity of forming contacts to the main channel portions of vertically stacked transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density by allowing for the vertical stacking of transistors, overcoming scaling limitations and enabling more compact and efficient 3D logic chip designs, thereby improving performance and density in semiconductor devices.
Implementation Method 1
S-D contacts are formed on respective S-D ends of the complex channel structure
Implementation Method 2
annealing to for silicide contacts from each of the S-D ends
Data Source
AI summary
A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.