U-Shaped Spacer Airgap Isolation in Stacked Nanosheet FETs
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Solution Overview
Problem
As nanosheet technology scales down, the challenge of isolating upper stack nanosheet transistors from lower stack nanosheet transistors becomes increasingly important due to interference between closely spaced devices.
Innovation Solution
A microelectronic structure with a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor, featuring an airgap between the upper and lower source/drain regions, with a U-shaped layer and additional liner layers strategically positioned to enhance isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If nanosheet technology is scaled down to reduce device size, then device density and integration are improved, but interference between upper and lower stack transistors increases
Solution Approach 1:
An airgap is introduced as an intermediary space between the upper and lower source/drain regions. This airgap acts as a mediator that physically separates the two stacks, preventing direct electrical and electrical-field interference while allowing the devices to remain in close proximity for high density integration.
Solution Approach 2:
The source/drain regions are segmented into distinct upper and lower portions with the airgap creating a physical division. This segmentation isolates the electrical fields of each stack, preventing coupling between upper and lower transistors while maintaining individual device functionality.
2Object-affected harmful factors
If an airgap is introduced to isolate upper and lower stacks, then interference between stacks is reduced, but device complexity increases
Solution Approach 1:
The U-shaped spacer and liner layers are merged to form an integrated isolation structure. The liner layers are deposited conformally on the spacer surfaces, creating a combined structure that provides both mechanical support and electrical isolation in a single integrated feature rather than separate components.
Solution Approach 2:
The airgap structure is formed through self-aligned processes where the spacer and liner layers automatically position themselves relative to the source/drain regions. The conformal deposition of liner layers on the spacer surfaces ensures proper positioning without additional alignment steps, reducing process complexity.
Data Source
AI summary
A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.