U-Shaped TFT Contacts With Self-Aligned Electrode Patterning
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Solution Overview
Problem
The challenge in fabricating thin-film transistors (TFTs) lies in the difficulty of patterning components at scaled dimensions, leading to variations in on and off currents due to edge roughness and pattern variations, which existing techniques fail to address effectively through self-aligned patterning.
Innovation Solution
The implementation of a U-shaped channel structure in TFTs, where a gate dielectric layer is formed above a substrate, and self-aligned source and drain electrodes are formed above the U-shaped channel, reducing variations and improving performance by using spacers and dummy oxides to align electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography patterning is used for TFT components at scaled dimensions, then device integration is achieved, but manufacturing precision deteriorates due to edge roughness and pattern variations
Solution Approach 1:
The method performs preliminary patterning actions by forming the gate electrode and gate dielectric layer before forming the channel and source/drain electrodes. This sequential preliminary action establishes reference structures that guide subsequent self-aligned patterning steps, ensuring precise positioning without requiring additional lithography alignment steps.
Solution Approach 2:
The patent implements self-aligned patterning where previously formed structures (gate electrode, gate dielectric) serve as alignment references for subsequent structures (channel, source/drain electrodes). Each structure automatically positions itself relative to the previous ones through conformal deposition and etching processes, eliminating the need for external lithography alignment and reducing edge roughness-induced variations.
2Area of moving object
If device dimensions are scaled down to improve integration, then transistor density increases, but manufacturing precision deteriorates due to increased sensitivity to edge roughness
Solution Approach 1:
The self-aligned patterning methodology allows each TFT component to automatically position itself relative to previously formed structures through conformal deposition and selective etching. This self-positioning mechanism eliminates lithography alignment errors and reduces sensitivity to edge roughness, maintaining dimensional control even as device dimensions are scaled down to increase transistor density.
Solution Approach 2:
The patent transitions from planar lithography-based patterning to a multi-dimensional self-aligned approach using conformal film deposition and vertical etching. By utilizing the vertical dimension for conformal coating and then transferring that pattern horizontally through etching, the method achieves superior dimensional control at scaled dimensions compared to conventional two-dimensional lithography.
3Manufacturing precision
If self-aligned patterning is implemented to improve manufacturing precision, then electrode alignment improves, but device complexity increases due to additional process steps
Solution Approach 1:
The patent merges multiple patterning operations into a unified self-aligned process flow. Instead of separately patterning the gate electrode, gate dielectric, channel, and source/drain electrodes using independent lithography steps, the method combines these operations into a sequential self-aligned process where each structure formation step automatically positions the next structure, reducing the total number of independent patterning operations.
Solution Approach 2:
The self-aligned patterning methodology serves multiple functions simultaneously: it positions the channel relative to the gate electrode, positions the source/drain electrodes relative to the channel, and ensures proper spacing and alignment throughout. This multi-functional approach eliminates the need for separate alignment operations for each structure, reducing overall process complexity despite the sequential nature of the steps.
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.