U-Shaped Trench Etching via Polysilicon Gate Barrier
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Solution Overview
Problem
Current methods for manufacturing U-shaped trenches in CMOS semiconductor devices are costly and prone to damaging the silicon substrate, with low etching rates and inadequate protection for the polysilicon gate, limiting their suitability for advanced semiconductor manufacturing.
Innovation Solution
A method involving the formation of a barrier layer on polysilicon gates, ion implantation to create doped silicon regions, and subsequent wet etching with hot phosphoric acid to form the U-shaped trench, which increases etching rate and protects the substrate and gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching is used to form the U-shaped trench with a hard mask layer, then the trench shape can be controlled, but the manufacturing cost increases and the silicon substrate is prone to damage
Solution Approach 1:
The patent applies preliminary action by depositing a silicon oxide barrier layer on the polysilicon gate surface before the trench etching process. This barrier layer is formed in advance to prevent damage to the polysilicon gate during subsequent etching operations, eliminating the need for costly hard mask layers and substrate protection measures while maintaining precise trench shape control.
Solution Approach 2:
The silicon oxide barrier layer serves as an intermediary protective layer between the etching process and the polysilicon gate. This intermediate layer prevents direct contact between the etching chemicals and the gate structure, reducing damage risk and manufacturing complexity while maintaining etching precision.
2Productivity
If dry etching is used to form the U-shaped trench, then the trench can be etched, but the etching rate is low and the silicon substrate is damaged
Solution Approach 1:
The patent applies local quality by creating a localized barrier layer specifically on the polysilicon gate surface where protection is needed, while leaving other areas accessible for efficient etching. The silicon oxide barrier layer provides targeted protection to the gate region without impeding the overall etching rate of the trench formation process.
Solution Approach 2:
The barrier layer is deposited in advance before etching, preparing the polysilicon gate surface to resist damage during the etching process. This preliminary protective measure enables faster etching rates without compromising substrate integrity, as the gate is already protected before the etching chemicals contact it.
3Productivity
If the hard mask layer is removed after trench formation, then the trench can be completed, but the polysilicon gate is damaged and manufacturing cost increases
Solution Approach 1:
The silicon oxide barrier layer acts as an intermediary protective layer during the entire trench formation process, eliminating the need for hard mask removal steps. This intermediate protection maintains gate integrity throughout manufacturing and removes costly and time-consuming demasking operations.
Solution Approach 2:
The barrier layer is formed in advance to provide continuous protection during trench etching, eliminating the need for subsequent hard mask removal operations. This preliminary protective measure maintains gate integrity throughout the process and improves manufacturing efficiency by removing demasking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances etching productivity, protects the polysilicon gate and substrate, and allows for precise control of trench depth and spacing, significantly improving the manufacturing process efficiency and reducing costs.
Implementation Method 1
ions are implanted into the exposed substrate. As a result, some doped silicon regions are formed in the silicon substrate
Implementation Method 2
The doped silicon regions are then removed by wet etching with hot phosphoric acid to form the U-shaped trench
Data Source
AI summary
The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.