U-Type Metal Gate Structure for Semiconductor Device
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Solution Overview
Problem
Conventional polysilicon gates in semiconductor devices face performance issues due to boron penetration and depletion effects, leading to inferior capacitance and driving force, while dual metal gate processes face complexity and reliability challenges, especially in high-temperature gate first processes.
Innovation Solution
A semiconductor device with a metal gate structure that includes a U-type metal layer between the gate dielectric and filling metal layers, where the topmost portion of the U-type metal layer is lower than the filling metal layer, fabricated using a gate last process to avoid high thermal budgets and improve filling reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then manufacturing process is simple, but performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal materials with different work functions. Specifically, it uses a first metal gate material for NMOS devices and a second metal gate material for PMOS devices, thereby improving device performance by eliminating boron penetration and depletion effects while maintaining manufacturing feasibility through the gate-last process
Solution Approach 2:
The patent segments the gate electrode into different materials for different device types within the same CMOS device. NMOS devices use a first metal gate material while PMOS devices use a second metal gate material, allowing each transistor type to have optimized electrical characteristics without requiring completely separate manufacturing processes
2Ease of manufacture
If gate first process is used, then manufacturing process is established, but high-temperature processes cause re-crystallization of high-K gate dielectric layer and Vfb roll-off issue
Solution Approach 1:
The patent inverts the conventional gate-first process sequence by adopting a gate-last process. Instead of forming the metal gate before source/drain regions, the metal gate is formed after source/drain regions are already in place. This inversion eliminates the need for subsequent high-temperature processes that would damage the high-K gate dielectric layer, thereby preventing re-crystallization and Vfb roll-off issues
3Reliability
If gate last process is used, then high heat budget is avoided, but filling reliability of gate trench becomes critical
Solution Approach 1:
The patent applies preliminary action by forming a barrier layer at the bottom and sidewalls of the gate trench before filling it with metal gate material. This barrier layer prevents metal diffusion into the source/drain regions and ensures controlled, reliable filling of the gate trench, addressing the critical filling reliability requirement of the gate-last process
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.