UART-Based Boundary Scan Testing for Memory Controllers

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Solution Overview

Problem

Conventional boundary scan testing of PCB-mounted memory sub-system controllers requires external specialized testers and dedicated connections, limiting accessibility and increasing costs, as well as PCB space and routing complexities.

Innovation Solution

Enabling boundary scan testing using a Universal Asynchronous Receiver/Transmitter (UART) connection, where a UART host provides test data to a TAP controller via the JTAG interface, allowing internal operation and reducing the need for external connections, thus facilitating testing without additional hardware or space constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional boundary scan testing is performed using external specialized testers, then testing capability is achieved, but device complexity and PCB space requirements increase

Engineering Contradiction:

Improvetesting capabilityVSAvoidPCB space and routing

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The controller performs boundary scan testing on itself by utilizing its own UART interface and processing resources. The controller receives test commands, executes boundary scan operations, and returns test results without requiring external specialized testing equipment, thereby eliminating the need for additional PCB test interfaces and reducing routing complexity

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The UART interface, originally designed for general communication purposes, is made multi-functional by enabling it to handle both normal operational communication and boundary scan testing. This allows the same hardware interface to serve dual purposes, eliminating the need for dedicated test interfaces and reducing overall device complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If external specialized testers are used for boundary scan testing, then comprehensive testing is achieved, but cost increases

Engineering Contradiction:

Improvetesting coverageVSAvoidtesting cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The controller autonomously performs boundary scan testing using its own processing unit and UART interface, eliminating the need for expensive external specialized testers. This self-testing capability maintains comprehensive testing coverage while significantly reducing manufacturing and testing costs by utilizing existing controller resources

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces expensive, specialized external testing equipment with the controller's own inexpensive UART interface and processing capabilities. This substitution uses readily available, low-cost components that are already part of the controller, thereby reducing overall testing cost while maintaining testing effectiveness

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Reliability

If dedicated test connections are implemented on PCB, then boundary scan testing is enabled, but PCB pin count and routing complexity increase

Engineering Contradiction:

Improvetesting accessibilityVSAvoidPCB pin count

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The UART interface pins are made multi-functional, serving both general communication purposes and boundary scan testing functions. This eliminates the need for dedicated test pins on the PCB, reducing the overall pin count requirement and simplifying PCB routing while maintaining full testing accessibility through the same interface

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11209483B2Controller accessible test access port controls

Publication Date: 2021.12.28 MICRON TECHNOLOGY INC

AI summary

Boundary scan test data and a command to initiate a boundary scan test are received via a universal asynchronous receiver-transmitter (UART). Based on receiving the command, a boundary scan test mode is initiated at a memory sub-system controller. A boundary scan test vector based on the boundary scan test data is synchronously streamed to a boundary scan chain. Test result data output by the scan chain is provided to a UART host via the UART.