UART Multiplexer Controller Redundancy via Combinational Logic

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Solution Overview

Problem

Computing systems face disruptions and errors due to the unavailability or busy state of baseband management controllers (BMCs) that control UART multiplexers, leading to failed or incomplete tasks, especially in multi-node systems where redundancy is lacking.

Innovation Solution

Implementing a system with multiple controllers that can prioritize and take over the management of a UART multiplexer, using combinational logic to determine the available controller and switch control signals to ensure continuous operation, allowing for redundancy and fault tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single controller manages the UART multiplexer, then the device complexity is low, but the reliability deteriorates when the controller is unavailable or busy

Engineering Contradiction:
Improvecontroller availabilityVSAvoidcontroller structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system segments the controller management function by introducing multiple independent controllers (primary and secondary) that can independently manage the UART multiplexer. Each controller has its own status signal and select control signal, dividing the single-point failure risk into multiple independent management paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system prepares a secondary controller in advance that can take over if the primary controller fails. The combinational logic circuit is pre-configured to monitor the primary controller's status signal and automatically switch to the secondary controller's select control signal when the primary becomes unavailable, providing fault tolerance before failure occurs.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If multiple controllers are implemented for redundancy, then the reliability improves, but the device complexity increases

Engineering Contradiction:
Improvefault toleranceVSAvoidcontroller management structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The combinational logic circuit serves as an intermediary that automatically manages the interaction between multiple controllers and the UART multiplexer. It monitors status signals from multiple controllers and automatically selects the appropriate select control signal, eliminating the need for complex software-based arbitration and reducing overall system complexity despite having multiple controllers.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements self-service through automatic failover mechanisms where the combinational logic circuit continuously monitors controller status and autonomously switches between controllers without requiring external intervention or complex coordination protocols, simplifying the management of multiple controllers.

Inventive Principle:
Principle #25Self-service

3Reliability

If controller priority switching is implemented, then the reliability improves during failures, but the ease of operation deteriorates due to automatic switching logic

Engineering Contradiction:
Improvecontinuous operationVSAvoidcontrol signal management
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system replaces manual or software-based controller selection with a hardware-level combinational logic circuit that automatically manages control signal routing. This hardware-based approach provides deterministic, real-time switching based on status signals, ensuring continuous operation while simplifying control signal management through automatic hardware-level arbitration.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20240356842A1System and method for managing a UART multiplexer connected to multiple hosts
Publication Date: 2024.10.24 QUANTA COMPUTER INC
  • US20240356842A1 patent drawing
  • US20240356842A1 patent drawing
  • US20240356842A1 patent drawing

AI summary

A computing system including two or more controllers, a universal asynchronous receiver-transmitter (UART) multiplexer, and a combinational logic circuit is provided. The two of more controllers include a first controller and a second controller. The first controller is configured to provide a first status signal and a first select control signal, and the second controller is configured to provide a second status signal and a second select control signal. The UART multiplexer is configured to provide UART output from at least a first UART input and a second UART input based on a UART select signal. The combinational logic circuit is configured to determine the UART select signal is one of the first select control signal or the second select control signal based at least in part on the first status signal and the second status signal.