UART Receiver Adaptive Sample Timing NCO

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Universal asynchronous receiver-transmitter (UART) links face frequency errors due to local clock generation differences and non-integer relationships between system clock and baud rate, leading to bit errors from cumulative errors.

Innovation Solution

A UART receiver with an adaptive sample timing circuit using a numerically-controlled oscillator (NCO) circuit, which adjusts sample timing based on accumulated clock and bit count values, eliminating the need for a pre-defined training pattern and accounting for count overflows, thereby addressing frequency errors and fractional baud rate relationships.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a pre-defined training pattern is used to adjust sample timing, then frequency errors can be corrected, but the device complexity and cost increase

Engineering Contradiction:

Improvesample timing accuracyVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The UART receiver automatically tracks and corrects frequency errors using the incoming data stream itself as the training source. The NCO circuit continuously adjusts sample timing based on detected data edges, eliminating the need for external training patterns or manual calibration while maintaining adaptive sample timing accuracy

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system dynamically changes the sample timing parameter in real-time using a numerically-controlled oscillator. The NCO adjusts the sampling phase and timing based on accumulated bit and clock counts, allowing continuous adaptation to frequency offsets without fixed training sequences

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If the system clock to baud rate relationship is non-integer, then flexibility is improved, but frequency errors and bit errors increase

Engineering Contradiction:

Improveclock to baud rate relationship flexibilityVSAvoidbit error rate

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The system implements continuous feedback through the NCO circuit, which monitors the relationship between system clock and baud rate using accumulated bit counts and clock counts. The NCO adjusts sample timing based on this feedback to compensate for frequency offsets caused by non-integer relationships, maintaining reliable communication despite flexible clock configurations

Inventive Principle:

Principle #23Feedback

3Device complexity

If adaptive sample timing is implemented without NCO, then device complexity is reduced, but frequency error tracking capability is lost

Engineering Contradiction:

Improvecircuit simplicityVSAvoidfrequency error tracking

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent replaces complex hardware phase-locked loop (PLL) circuits with a numerically-controlled oscillator implementation that uses simple digital counters and a lookup table. This substitution maintains frequency tracking capability while significantly reducing circuit complexity and making the solution suitable for integrated circuit implementation

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11341015B2UART receiver with adaptive sample timing control using a numerically-controlled oscillator

Publication Date: 2022.05.24 TEXAS INSTRUMENTS INC

AI summary

A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.