UART Sampling Controller Variable Clock Edge Assignment
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Solution Overview
Problem
Conventional UART modules require multiple clock signal generators or complex frequency synthesis structures to handle various baud rates, especially those that are not integer multiples of each other, leading to increased costs and complexity.
Innovation Solution
A UART module with a sampling controller that assigns a variable number of active edges in a clock signal to respective bits in a serial data signal, allowing sampling based on a locally generated clock signal that may not be a multiple of the baud rate, and utilizing a single clock signal for different baud rates, including those required by GSM standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock signal generators or complex frequency synthesis structures are used to handle various baud rates, then the UART module can support different baud rates, but the device complexity and cost increase
Solution Approach 1:
The patent applies universality by designing a single clock signal generator that can serve multiple baud rates through a variable divider mechanism. The clock signal generator is configured to generate a single base clock frequency that is then divided by variable divider values to produce the required sampling frequencies for different baud rates, eliminating the need for multiple separate clock generators.
Solution Approach 2:
The patent utilizes parameter changes by varying the divider value in the frequency division circuit. The divider value can be changed based on the required baud rate, allowing the same hardware circuit to adapt to different communication speeds. This is achieved through a control mechanism that adjusts the divider value dynamically or selectively.
2Adaptability or versatility
If multiple clock signal generators are used for different baud rates, then various baud rates can be supported, but the cost increases
Solution Approach 1:
The patent implements multi-functionality through a single universal clock signal generator that handles multiple baud rates. By consolidating multiple clock generator functions into one circuit with variable division capability, the patent reduces component count and manufacturing complexity while maintaining the ability to support various baud rates.
Solution Approach 2:
The patent merges the functions of multiple clock signal generators into a single integrated circuit. The frequency division circuit combines the clock generation and frequency adjustment functions in one block, reducing the overall component count and simplifying the bill of materials, thereby reducing manufacturing costs.
3Device complexity
If a single clock signal is used for various baud rates, then cost and complexity are reduced, but the sampling frequency must be precisely controlled
Solution Approach 1:
The patent maintains sampling frequency precision by implementing a variable frequency division mechanism. The base clock frequency is divided by precisely controllable divider values that are selected based on the required baud rate. This ensures that the sampling frequency remains accurate even when using a single clock signal source.
Solution Approach 2:
The patent incorporates feedback mechanisms to ensure accurate frequency division. The control circuit monitors the required baud rate and adjusts the divider value accordingly, providing feedback control to maintain precise sampling frequencies. This feedback ensures that timing accuracy is maintained despite using a single clock source.
Data Source
AI summary
A universal asynchronous receiver-transmitter module that includes a sampling controller that assigns a variable number of active edges in a clock signal to respective bits in a serial data signal. A serial data reception path derives a bit from the serial data signal on the basis of the variable number of active edges that the sampling controller has assigned to the bit.