UART Sampling Counter Pattern for Low Power Clock
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Solution Overview
Problem
UART timing issues lead to data corruption due to limited error budgets, requiring high-frequency reference clocks that are costly, power-intensive, and increase die size, and often necessitate complex NCO or PLL circuitry.
Innovation Solution
Pre-calculated counter patterns for the UART reference clock, based on data rate and frequency, are used to determine when to sample serial data streams, allowing sampling within the data eye without the need for high-frequency clocks, thus enabling the use of system clocks and reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency UART reference clock is used to allow larger error budgets and maintain accurate data sampling, then measurement precision is improved, but device complexity increases due to the need for NCO or PLL circuitry
Solution Approach 1:
The patent pre-calculates counter patterns for different baud rates and reference clock frequencies, storing them in a lookup table before operation. During runtime, the system simply retrieves the pre-computed counter pattern based on the desired baud rate and reference clock frequency, eliminating the need for complex real-time calculations or specialized NCO/PLL circuitry while maintaining accurate sampling timing
Solution Approach 2:
The patent creates a simplified model of the timing relationship by pre-computing and storing counter patterns that represent the optimal sampling points for various baud rates and clock frequencies. This copied timing information is then directly applied during operation, replacing the need for complex dynamic timing generation circuits
2Reliability
If a high-frequency UART reference clock is used to maintain accurate data sampling within the data eye, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent changes the approach from using a fixed high-frequency reference clock to dynamically selecting counter patterns based on the relationship between baud rate and reference clock frequency. This allows the system to use lower-frequency system clocks while maintaining reliable sampling by adjusting the counter patterns to achieve accurate mid-bit sampling points
3Measurement precision
If a high-frequency UART reference clock is used to achieve fine resolution for data sampling, then measurement precision is improved, but die size increases
Solution Approach 1:
The patent makes the counter pattern generation system universal by creating a lookup table that covers multiple baud rates and reference clock frequency combinations. This single pre-computed table serves all timing requirements, eliminating the need for separate hardware timing generators for different operating conditions and reducing overall die size
Solution Approach 2:
The patent replaces expensive, large-area specialized timing circuitry (NCO, PLL) with a simple, compact lookup table implementation that can be efficiently stored in ROM or RAM. The lookup table provides the necessary timing precision at a fraction of the cost and area of traditional hardware timing generators
4Productivity
If the UART reference clock frequency is increased to allow larger error budgets, then productivity is improved through finer sampling resolution, but use of energy increases
Solution Approach 1:
The patent pre-calculates and stores the optimal counter patterns that achieve fine sampling resolution for various baud rates and reference clock frequencies. This allows the system to maintain high productivity with fine sampling resolution while using lower-power reference clocks by simply retrieving the pre-computed timing information instead of generating it dynamically with high-frequency clocks
Data Source
AI summary
In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.