UART Timer Module for USART Clock Duplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data processing systems with only UART modules lack efficient communication with USART modules, relying on resource-intensive software 'bit banging' for interface, which increases processing overhead.
Innovation Solution
A data processing system that enables half-duplex asynchronous USART communication using a UART module coupled with a timer module to generate a USART clock signal, allowing direct communication between UART and USART modules without bit banging, by using a baud generator to produce the correct baud rate and a timer to duplicate the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software bit banging is used to interface UART module with USART module, then communication between UART and USART is enabled, but processing overhead increases
Solution Approach 1:
A timer module is introduced as an intermediary component between the UART module and USART module. The timer module generates the clock signal that the UART module needs to operate in synchronous USART mode, thereby enabling UART-USART communication without requiring software bit banging. This intermediary hardware component resolves the contradiction by providing the necessary clock signal hardware-wise rather than through software overhead.
Solution Approach 2:
The patent replaces the software-based bit banging mechanism with a hardware-based timer module. Instead of using software instructions to generate clock signals and manage communication timing (mechanical/software system), a dedicated hardware timer module generates the clock signal directly. This substitution eliminates the processing overhead associated with software bit banging while maintaining communication compatibility.
2Device complexity
If UART module operates in asynchronous mode without clock signal, then hardware complexity is reduced, but communication speed and synchronization capability are limited
Solution Approach 1:
The patent enables the UART module to dynamically switch between asynchronous and synchronous communication modes. By introducing a timer module that can generate clock signals on demand, the system allows the UART module to operate in synchronous mode when high-speed communication is needed, while retaining the ability to operate in asynchronous mode when hardware simplicity is preferred. This dynamic capability resolves the contradiction by allowing the system to adapt its complexity and performance characteristics based on communication requirements.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A data processing system includes a universal asynchronous receive/transmit (UART) module and timer module. The UART module has a first input terminal for receiving an input clock signal, a second input terminal for receiving a receive data signal, and an output terminal for providing a transmit data signal. The receive data signal and the transmit data signal use a baud rate based clock signal determined using the input clock signal, and wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter (USART) module. The timer module is coupled to receive the input clock signal. The timer module provides a duplicate baud rate clock signal for communication to the USART module. The duplicate baud rate clock signal is substantially the same as the baud rate based clock signal.