UART Transfer Controller Ring Buffer FPGA Interrupts
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Solution Overview
Problem
Current UART systems face inefficiencies in data transfer and processor demand due to limited buffer sizes and the need for frequent processor intervention, leading to slow communication and high CPU utilization.
Innovation Solution
A transfer controller system that includes ring buffers and descriptors to manage data transfer between the processor, system memory, and UARTs, allowing for efficient data handling and reduced CPU involvement through the use of Field Programmable Gate Arrays (FPGAs) and PCI buses, enabling asynchronous data processing and interrupt management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor immediately processes each transmitted byte, then data reliability is maintained, but system speed decreases and processor overhead increases
Solution Approach 1:
The patent implements a FIFO buffer that preliminarily stores incoming bytes before processor processing. This allows data to be captured and held in the buffer immediately upon reception, ensuring no data is lost, while the processor can process at its own pace without real-time pressure, thus resolving the contradiction between data reliability and system speed.
2Loss of information
If the processor periodically polls the UART, then data can be detected, but processor overhead and interrupt processing time increase
Solution Approach 1:
The patent implements an interrupt-driven mechanism where the UART controller automatically generates interrupts when data is available in the FIFO buffer. This self-service approach eliminates the need for continuous processor polling, as the system automatically notifies the processor only when necessary, reducing processor overhead and interrupt processing time while ensuring data is detected promptly.
3Adaptability or versatility
If the processor scans incoming data for special values, then special processing can be performed, but CPU utilization increases
Solution Approach 1:
The patent extracts the special value scanning function from the main processor and implements it as a separate interrupt handler or background task. This allows the processor to focus on primary processing tasks while a dedicated mechanism handles the scanning for special values, reducing overall CPU utilization while maintaining the capability to perform special processing when needed.
4Productivity
If larger FIFO buffers are used, then communication speed increases and processor polling frequency decreases, but buffer management complexity increases
Solution Approach 1:
The patent introduces a dedicated buffer manager component that mediates between the large FIFO buffer and the processor. This intermediary handles buffer allocation, data transfer coordination, and status monitoring, allowing the system to utilize large buffers for high-speed communication while the buffer manager simplifies the complexity of buffer management by providing a standardized interface.
Data Source
AI summary
A system and method of transferring characters from a first device through a buffer memory to a second device. A descriptor is read and a buffer address and a buffer length are extracted from the descriptor, wherein the buffer address and buffer length define a buffer of data stored in the first device. The data stored in the buffer is transferred from the buffer to the buffer memory, and from there to the second device. A check is made to determine if the descriptor should be closed and, if the descriptor should be closed, an indication is made that the descriptor is closed.