UART Interface Circuit Dynamic Wakeup Timing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In UART technology, when an electronic device is woken up by UART data, the existing systems face errors due to the 'wakeup stable time' being longer than the start-bit cycle, leading to limitations in baud rate.
Innovation Solution
A UART interface circuit with a baud-rate generating circuit, control circuit, and receiving circuit that compares the start-bit cycle with the wakeup stable time to determine when to start capturing UART data, allowing data capture from the start bit or first data bit after the wakeup stable time has terminated, and adjusts the capture point based on the relationship between the start-bit cycle and wakeup stable time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the electronic device waits for the wakeup stable time before capturing UART data, then the system stability is improved, but the baud rate is limited and reception errors occur when wakeup stable time exceeds start-bit cycle
Solution Approach 1:
The control circuit performs preliminary comparison between the wakeup stable time and start-bit cycle before data capture begins. This allows the system to pre-determine the optimal capture timing, ensuring that data capture is synchronized with the actual UART data arrival rather than relying on fixed waiting periods, thereby preventing reception errors while maintaining system stability
Solution Approach 2:
The invention dynamically adjusts the data capture timing based on the relationship between wakeup stable time and start-bit cycle. When wakeup stable time is longer than start-bit cycle, the system captures from the first data bit; when shorter, it captures from the start bit. This dynamic adaptation allows the system to maintain both stability and reception accuracy under varying conditions
2Stability of the object's composition
If the wakeup stable time is extended to ensure system stability, then system reliability is improved, but the baud rate must be limited which reduces communication speed
Solution Approach 1:
The invention changes the capture timing parameter dynamically based on the comparison result between wakeup stable time and start-bit cycle. This parameter adjustment allows the system to support higher baud rates without sacrificing stability, as the capture timing is optimized rather than constrained by fixed stable time requirements
3Speed
If the electronic device starts capturing data immediately after wakeup, then the communication speed is improved, but reception errors occur due to system instability
Solution Approach 1:
The control circuit uses feedback from the wakeup stable time circuit and baud-rate generating circuit to determine the optimal capture timing. This feedback mechanism ensures that data capture only begins when the system is ready, preventing reception errors while minimizing unnecessary waiting time, thus maintaining both speed and reliability
Data Source
AI summary
An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.