Semiconductor Package Terminal Fill Structure for Stress Relief

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving structural reliability and maintaining a short electrical connection path between the chip pad and the connection terminal, often resulting in stress concentration during fabrication that leads to cracks and peeling phenomena.

Innovation Solution

The semiconductor package design incorporates a redistribution pattern and under bump metal (UBM) with dummy holes and grooves that distribute stress into these dummy spaces, allowing the connection terminal to fill these areas, thereby enhancing structural reliability and maintaining a short electrical connection path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a short electrical connection path is implemented between chip pad and connection terminal, then electrical connection efficiency is improved, but structural reliability deteriorates due to stress concentration during fabrication

Engineering Contradiction:
Improveelectrical connection efficiencyVSAvoidstructural reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The connection terminal is segmented into a functional portion (for electrical connection) and a dummy portion (for stress absorption). This segmentation allows the terminal to simultaneously achieve short electrical path length while distributing fabrication stress to the dummy portion, resolving the contradiction between connection efficiency and structural reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy portion acts as an intermediary element between the chip pad and the functional connection terminal. It absorbs stress during fabrication processes (such as reflow soldering) and prevents stress concentration at the critical electrical connection path, thereby maintaining both short electrical path and high structural reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If stress distribution structures are added to improve structural reliability, then fabrication stress is reduced, but device complexity increases

Engineering Contradiction:
Improvestructural reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy portion is merged with the functional connection terminal to form a single integrated structure. This merging approach allows stress distribution functionality to be added without requiring separate components or complex assembly processes, thereby improving structural reliability while minimizing increases in device complexity

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If dummy portions are added to distribute stress, then structural reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestructural reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The dummy portion is designed with specific local characteristics (extended length, specific geometry) that are optimized for stress absorption. By concentrating the stress-absorbing function in this specific local region with well-defined geometry, the design achieves high structural reliability while using conventional manufacturing tolerances, rather than requiring high precision across the entire structure

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11769743B2Semiconductor package
Publication Date: 2023.09.26 SAMSUNG ELECTRONICS CO LTD
  • US11769743B2 patent drawing
  • US11769743B2 patent drawing
  • US11769743B2 patent drawing

AI summary

A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.