Semiconductor UBM Eave Structure Over-Etching Control
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Solution Overview
Problem
The existing methods for forming an under-bump metal (UBM) layer between a pad electrode and a solder bump in semiconductor devices face challenges with over-etching, leading to reduced bonding intensity and reliability due to isotropic etching, which increases production time and costs.
Innovation Solution
A semiconductor device and manufacturing method that incorporate a main metal layer with eave portions at its outer edge, allowing for controlled over-etching during the etching process of the underlying metal layer, using a chemical solution with a slower etching rate on the eave portions to prevent over-etching and maintain bonding integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If isotropic etching is used to remove the metal seed layer, then the etching process is simple and fast, but over-etching occurs leading to corrosion of the pad electrode and reduced bonding reliability
Solution Approach 1:
The patent applies local quality by creating an eave portion with a different structure at the outer edge of the main metal layer. This eave portion has a larger diameter than the opening in the mask, providing a localized protective protrusion only where needed at the edges, while the center region maintains normal etching. This localized structural modification prevents over-etching at the critical edge regions without affecting the overall etching efficiency.
Solution Approach 2:
The eave portion acts as a beforehand cushioning structure that compensates for the inherent over-etching tendency of isotropic etching. By providing this extra metal protrusion at the outer edge before etching occurs, the patent creates a buffer zone that absorbs the lateral etching attack, preventing it from reaching the pad electrode. This prior cushioning allows the use of simple isotropic etching while maintaining reliability.
2Reliability
If oxidation processing is performed to prevent over-etching of the metal seed layer, then bonding reliability is improved, but production time increases significantly (24 hours) and cost increases
Solution Approach 1:
The eave portion functions as a disposable protective structure that is removed during the etching process. Instead of using expensive and time-consuming oxidation processing to create a protective layer, the patent uses a simple geometric modification (the eave portion) that serves its protective function temporarily during etching and is then eliminated. This approach is both cheaper and faster than oxidation.
Solution Approach 2:
The patent changes the geometric parameters of the metal layer by creating the eave portion with a larger diameter than the mask opening. This parameter change (increasing the outer diameter of the metal layer) provides the necessary protection against over-etching without requiring chemical modification through oxidation. The parameter change alone is sufficient to prevent pad electrode corrosion.
3Manufacturing precision
If the metal seed layer is formed on the entire wafer surface, then uniform coverage is achieved, but electrical connection between pad electrodes occurs and requires subsequent removal
Solution Approach 1:
The patent segments the metal layer formation process into two distinct stages: first forming the metal seed layer uniformly across the entire wafer surface, then forming the main metal layer with patterned openings that segment the continuous metal layer into isolated regions over each pad electrode. This segmentation approach maintains the simplicity of uniform deposition while achieving the necessary electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the bonding adhesion between pad electrodes and solder bumps, prevents corrosion, and maintains high reliability while reducing production time and costs by allowing for precise control of over-etching and stress reduction during solder reflow.
Implementation Method 1
etching which removes a top layer of the underlying metal layer is performed, and then the main metal layer is formed in the opening
Implementation Method 2
A formation of the metal seed layer is performed by PVD (physical vapor deposition) and CVD (chemical vapor deposition) over an entire surface of a wafer
Implementation Method 3
A formation of the metal seed layer is performed by PVD (physical vapor deposition) and CVD (chemical vapor deposition) over an entire surface of a wafer
Implementation Method 4
a main metal layer made of, for example, Ni and the like is formed on the metal seed layer by electrolytic plating in which the metal seed layer is used as an electrode
Data Source
AI summary
A semiconductor device includes a first semiconductor electronic component which includes a pad electrode, a solder bump, and a metal layer between a pad and solder that is configured to have an underlying metal layer formed between the pad electrode and the solder bump and connected to the pad electrode, and a main metal layer formed on the underlying metal layer, and in which the main metal layer has an eave portion at an outer edge portion thereof.