Bumped Wafer Test Structure With UBM Extension

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Solution Overview

Problem

The existing methods for testing bumped semiconductor structures often result in excessive damage to the solder bumps and solder buildup due to direct contact with probe needles, leading to electrical failures and internal voids, which complicates the manufacturing process and increases costs.

Innovation Solution

A semiconductor structure is designed with an under bump metallurgy (UBM) extension that allows for electrical connectivity without direct contact with the solder bump, using openings in insulation layers to expose the UBM for testing, thereby preventing damage and solder buildup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a probe needle is used to contact the top of the solder bump for testing, then electrical connectivity for testing is achieved, but excessive bump damage and solder buildup occur

Engineering Contradiction:
Improvetesting reliabilityVSAvoidbump damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary conductive structure (extended UBM or separate conductive layer) that mediates between the probe needle and the solder bump. This intermediary allows electrical contact to be made at a location away from the bump top surface, thereby enabling testing while preventing direct mechanical contact and damage to the vulnerable bump structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extends the conductive path from the vertical dimension (direct contact with bump top) to the lateral dimension (contact with extended UBM or separate conductive layer). By moving the contact point laterally away from the bump center, the design enables testing without the needle contacting the bump top surface, thus avoiding damage while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If direct contact testing with the bump top is performed, then testing can be conducted, but internal voids and electrical failures result

Engineering Contradiction:
Improvetesting efficiencyVSAvoidbump integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The extended UBM or separate conductive layer serves as a mediator that enables testing functionality while protecting the bump integrity. This intermediary structure allows the testing process to proceed efficiently without compromising the mechanical and electrical integrity of the solder bump, thus avoiding internal voids and electrical failures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the electrical contact function from the mechanical bump structure. By creating a separate conductive path through extended UBM or an additional conductive layer, the design separates the testing contact function from the bump itself, allowing efficient testing while preserving bump integrity and avoiding damage-related defects.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If solder buildup on the probe needle occurs, then subsequent bump damage is caused, but testing continuity is disrupted

Engineering Contradiction:
Improvetesting operationVSAvoidsolder buildup
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary conductive structure that acts as a sacrificial or non-critical contact point for the probe needle. By designing the contact area as extended UBM or a separate conductive layer rather than the bump top, the system allows solder buildup to occur on the intermediary without causing damage to critical bump structures, thus maintaining testing operation continuity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8203145B2Structure for bumped wafer test
Publication Date: 2012.06.19 STATS CHIPPAC LTD
  • US8203145B2 patent drawing
  • US8203145B2 patent drawing
  • US8203145B2 patent drawing

AI summary

A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.