Solder Bump Interconnect UBM Geometry Optimization
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Solution Overview
Problem
The semiconductor industry faces challenges with the mechanical and thermo-mechanical stability of solder bump interconnects due to the sensitivity of rigid non-leaded solder compositions to thermal cycling and mechanical shock, particularly in flip chip and wafer-level chip-scale packaging, where smaller feature sizes and reduced IO pad sizes lead to instability and inconsistency.
Innovation Solution
The solution involves optimizing the geometry of the under bump metal (UBM) and polymer layers in the solder bump interconnect structure by adjusting the diameter ratios of the device pad, polymer opening, and UBM to improve even force distribution under thermal and mechanical stress, including specific ratios for the UBM and polymer opening diameters, and the landing pad to UBM diameter ratios, allowing for enhanced mechanical and thermo-mechanical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-leaded solder compositions are used, then environmental compliance is improved, but sensitivity to thermal cycling and mechanical shock increases
Solution Approach 1:
The patent applies beforehand cushioning by introducing a compliant under-bump metal layer between the rigid non-leaded solder bump and the substrate. This compliant layer acts as a shock-absorbing interface that prevents direct transmission of thermal and mechanical stresses to the brittle solder joint, thereby protecting the environmentally compliant non-leaded solder from failure under thermal cycling and drop conditions.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer interconnect structure consisting of the non-leaded solder bump, compliant under-bump metal layer, and substrate. This composite structure combines the environmental benefits of non-leaded solder with the mechanical flexibility of the compliant metal layer, achieving both environmental compliance and improved thermo-mechanical reliability.
2Productivity
If smaller feature sizes and reduced IO pad sizes are used, then device integration is improved, but mechanical and thermo-mechanical stability of solder bumps deteriorates
Solution Approach 1:
The patent applies local quality by providing the compliant under-bump metal layer specifically at the location of each solder bump, rather than uniformly across the entire device. This localized compliance structure is positioned precisely where the rigid non-leaded solder bumps make contact with the substrate, providing targeted mechanical support and stress relief exactly where needed to maintain stability in miniaturized devices.
Solution Approach 2:
The compliant under-bump metal layer serves as beforehand cushioning by being pre-positioned between the small rigid solder bump and the substrate before any thermal or mechanical stress is applied. This pre-positioned compliant layer absorbs and distributes stresses that would otherwise concentrate on the small bump-substrate interface, thereby maintaining mechanical and thermo-mechanical stability despite reduced feature sizes.
3Reliability
If rigid non-leaded solder compositions are used, then environmental compliance is improved, but drop test performance and reliability under mechanical shock deteriorates
Solution Approach 1:
The patent implements beforehand cushioning by placing a compliant under-bump metal layer between the rigid non-leaded solder bump and the substrate. This compliant layer acts as a shock-absorbing interface that prevents direct transmission of impact forces from drops to the brittle solder joint, thereby protecting the environmentally compliant non-leaded solder from mechanical failure while maintaining environmental compliance.
Solution Approach 2:
The compliant under-bump metal layer serves as an intermediary between the rigid non-leaded solder bump and the substrate. This intermediate layer mediates the mechanical interaction by absorbing and distributing impact forces, preventing direct stress concentration at the solder-substrate interface and thereby improving drop test performance while maintaining environmental compliance.
4Productivity
If the entire area of the semiconductor device is used for forming bond pads, then the number of electrical connections is improved, but the complexity of the interconnect structure increases
Solution Approach 1:
The patent applies segmentation by dividing the interconnect structure into distinct functional layers: the bond pad layer, the compliant under-bump metal layer, and the substrate. This segmented approach allows each layer to be optimized independently for its specific function while maintaining overall system simplicity, enabling increased connection density without proportionally increasing overall structural complexity.
Data Source
AI summary
A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.