Homogeneous UBM Structure for Thermal Stress Reduction
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Solution Overview
Problem
Conventional semiconductor packaging techniques face stress issues due to differing coefficients of thermal expansion between various layers, leading to potential solder failure and cracks in the joint area.
Innovation Solution
The implementation of an under-bump metallization (UBM) structure with buffer layers and conductor pads on substrates to provide a stable electrical connection, reducing thermal stress by using a single material property and redistributing stress across the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging techniques with multiple layers of different materials are used to achieve electrical connections, then integration density and connectivity are improved, but thermal stress and reliability deteriorate due to differing coefficients of thermal expansion
Solution Approach 1:
The patent applies homogeneity by using a single material (e.g., tungsten or copper) for both the contact plug and the underlying contact pad, eliminating material interfaces that cause thermal expansion mismatch. This single-material approach ensures uniform thermal expansion characteristics throughout the vertical stack, preventing stress concentration and crack formation at material boundaries while maintaining high integration density through direct through-substrate connections.
2Adaptability or versatility
If solder bumps are used to provide electrical connections between substrates, then connectivity and assembly flexibility are improved, but stress concentration and crack formation worsen due to CTE mismatch between layers
Solution Approach 1:
The patent eliminates the heterogeneous material stack by using uniform conductive material (tungsten or copper) from the contact plug through the conductive pad, removing the solder bump interface that causes stress concentration. This homogeneous structure maintains assembly flexibility through direct bonding while eliminating the weak point where cracks typically initiate due to CTE mismatch between solder and substrate materials.
Solution Approach 2:
The patent extracts and removes the solder bump element from the connection structure, replacing it with a direct through-substrate contact plug and pad configuration. This extraction eliminates the source of stress concentration and crack formation associated with solder joints, while the direct connection maintains electrical connectivity and assembly versatility through alternative bonding methods.
3Productivity
If multiple material layers with different CTEs are stacked to create interconnections, then electrical connectivity and packaging functionality are improved, but thermal stress and crack risk increase in the joint area
Solution Approach 1:
The patent applies homogeneity by using a single material composition for the vertical interconnection structure (contact plug and contact pad), eliminating the multi-layer material stack that generates thermal stress. This uniform material approach ensures consistent thermal expansion behavior throughout the connection path, preventing stress accumulation and crack formation while maintaining high packaging throughput through efficient direct connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces thermal stress between conductive bumps/balls and substrates, improving the reliability of electrical connections and minimizing solder failure, with simulation results showing a stress reduction of at least 32% in the interface area.
Implementation Method 1
The various layers making up these interconnections typically have different coefficients of thermal expansion (CTEs). As a result, a relatively large stress may be exhibited on the joint area
Data Source
AI summary
An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.