Strip-Shaped UBM Structure for InFO IPD ESR Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high performance and reliability in integrated fan-out (InFO) packages due to limitations in under-bump metallization (UBM) structures, particularly in integrating passive devices (IPDs) with high density and reduced equivalent series resistance (ESR) and equivalent series inductance (ESL), while also addressing manufacturing issues like solder bridging and pre-fill voids.

Innovation Solution

The design incorporates strip-shaped and comb-shaped conductive patterns in the UBM structure of IPDs, which are parallel or perpendicular to the top metallization layer, providing high coverage ratios and interleaved power/ground patterns to reduce ESR and ESL, and modified conductive patterns in the InFO package to prevent solder bridging and pre-fill voids.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional UBM structures are used in InFO packages, then manufacturing is simpler, but ESR and ESL are higher and reliability is reduced

Engineering Contradiction:
ImproveIPD performance and reliabilityVSAvoidUBM structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The UBM structure is segmented into multiple conductive patterns (strip-shaped and comb-shaped) with different orientations. These segmented patterns are interleaved to create multiple parallel current paths, which reduces ESR and ESL while maintaining manufacturing feasibility through standardized fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from conventional planar UBM patterns to three-dimensional interleaved structures with conductive patterns extending in multiple dimensions. The strip-shaped and comb-shaped patterns are positioned at different heights and orientations, creating a multi-dimensional conductive network that reduces electrical resistance and inductance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If conductive patterns are added to reduce ESR and ESL, then IPD performance improves, but manufacturing complexity increases

Engineering Contradiction:
ImproveESR and ESL reductionVSAvoidManufacturing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The strip-shaped and comb-shaped conductive patterns are merged into a single integrated UBM structure that is formed in one fabrication process. This combined structure achieves ESR and ESL reduction while avoiding the need for separate manufacturing steps, thereby maintaining ease of manufacture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention changes the geometric parameters of the conductive patterns (shape, orientation, spacing) to optimize electrical performance. By carefully controlling these parameters during a single fabrication process, the structure achieves low ESR and ESL without increasing manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If modified conductive patterns are used to prevent solder bridging, then manufacturing yield improves, but ESR may increase

Engineering Contradiction:
ImproveManufacturing yieldVSAvoidESR
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The UBM structure employs local quality variations where conductive patterns are strategically positioned and dimensioned to provide different functions in different regions. Areas with tighter spacing prevent solder bridging, while interleaved patterns in other regions maintain low ESR and ESL, achieving both manufacturing yield and electrical performance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11631658B2Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device
Publication Date: 2023.04.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11631658B2 patent drawing
  • US11631658B2 patent drawing
  • US11631658B2 patent drawing

AI summary

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.