Multi-Layered UBM With Insulating Buffer Layer for Stress Reduction

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Solution Overview

Problem

Semiconductor devices face thermal and mechanical stress issues, particularly in fine pitch bumps on low dielectric constant wafers, leading to bump cracking, delamination, and interconnect defects during manufacturing and reliability testing, which decrease production yield and increase costs.

Innovation Solution

A multi-layered Under Bump Metallization (UBM) structure is implemented with an intermediate insulating buffer layer between conductive layers to distribute and reduce thermal and mechanical stress on contact pads and bumps, using materials like polyimide, benzocyclobutene, and dielectric materials to form a conformal buffer layer that alleviates stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional UBM structure is used, then the manufacturing process is simple, but thermal and mechanical stress causes bump cracking and delamination

Engineering Contradiction:
Improvebump integrityVSAvoidUBM structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The UBM structure is divided into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) separated by insulating buffer layers. This segmentation allows each layer to independently manage stress and thermal expansion, preventing bump cracking and delamination while maintaining overall structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulating buffer layers are introduced as intermediary elements between the conductive layers. These buffer layers act as stress-relief interfaces that accommodate thermal expansion differences and mechanical stress, preventing direct stress transmission that would cause bump failure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If fine pitch bumps are used, then the device density increases, but thermal and mechanical stress increases causing defects

Engineering Contradiction:
Improvedevice densityVSAvoidinterconnect reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The multi-layered UBM structure segments the stress path, allowing fine pitch bumps to be supported by distributed stress management across multiple conductive and insulating layers, thereby maintaining both high density and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The structure changes the physical parameters of the UBM system by introducing layers with different mechanical and thermal properties. The insulating buffer layers have lower thermal conductivity and different expansion coefficients, which modifies the overall stress distribution to accommodate fine pitch requirements.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If low dielectric constant wafers are used, then the signal integrity improves, but mechanical stress increases causing delamination

Engineering Contradiction:
Improvesignal integrityVSAvoidadhesion strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The insulating buffer layers serve as intermediary structures between the low-k dielectric and the conductive layers. These buffer layers have intermediate mechanical properties that bridge the mismatch between the soft low-k material and the rigid conductive layers, preventing delamination while preserving signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The UBM structure creates a composite material system combining conductive layers, insulating buffer layers, and low-k dielectric. This composite structure leverages the complementary properties of each material to achieve both signal integrity and mechanical adhesion.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS9252093B2Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer
Publication Date: 2016.02.02 STATS CHIPPAC MANAGEMENT PTE LTD
  • US9252093B2 patent drawing
  • US9252093B2 patent drawing
  • US9252093B2 patent drawing

AI summary

A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.