Semiconductor Package UBM Layer Embedding in Passivation

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Solution Overview

Problem

The existing semiconductor package manufacturing processes face challenges with warpage and low cleanliness, leading to reduced process quality and yield, particularly in forming the under bump metallurgy (UBM) layer, which requires a separate carrier and dedicated line, and has high cleanliness requirements.

Innovation Solution

A semiconductor package design where the UBM layer is formed before the redistribution layer, with UBM pads protruding from the passivation layer, and UBM vias integrated with the redistribution layer, allowing for a simplified manufacturing process and improved reliability by embedding the UBM layer partially within the passivation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the UBM layer is formed after the package process using a separate carrier and dedicated line, then the UBM layer can be formed on the lower surface of the package, but the process complexity increases and productivity decreases

Engineering Contradiction:

ImproveUBM layer reliabilityVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The UBM layer is formed in advance on the connection member before the semiconductor chip mounting and package molding processes. This preliminary formation eliminates the need for subsequent carrier and dedicated line processes, reducing process complexity while maintaining UBM layer quality and reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The UBM layer formation process is merged with the connection member manufacturing process. By forming the UBM layer on the connection member before chip mounting, the patent combines multiple processes into one, eliminating the need for separate carrier and dedicated line processes

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If the UBM layer is formed after the package process, then the UBM layer can be formed on the lower surface, but the manufacturing cost increases due to separate carrier and dedicated line requirements

Engineering Contradiction:

ImproveUBM layer reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The UBM layer is formed in advance on the connection member before chip mounting and package molding. This preliminary action eliminates the need for expensive separate carrier and dedicated line processes, reducing manufacturing cost while maintaining UBM layer reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The UBM layer formation is merged with the connection member manufacturing process, eliminating the need for separate carrier and dedicated line infrastructure, thereby reducing capital expenditure and manufacturing cost

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If the UBM layer is formed after the package process in a low cleanliness environment, then the process can be completed, but the process quality and yield are reduced

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidprocess quality

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The UBM layer is formed in advance on the connection member before chip mounting and package molding in a high cleanliness environment. This preliminary formation avoids subsequent exposure and plating processes in low cleanliness environments, ensuring high process quality and yield while maintaining manufacturing efficiency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent converts the potential harm of low cleanliness environments by performing all high cleanliness要求的 processes (exposure, plating) in advance when the environment is controlled, then proceeding with chip mounting and molding in less controlled environments without compromising quality

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11189552B2Semiconductor package

Publication Date: 2021.11.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.