UBM Layer Structure for Thermal Stress Relief in Wafer-Level Packages
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Solution Overview
Problem
Wafer-level semiconductor packages face stress and reliability degradation due to differences in thermal expansion coefficients between the package and the main board, leading to potential cracks in the solder bump and failures.
Innovation Solution
A wafer-level semiconductor package design that includes a semiconductor chip with a redistribution layer, an under bump metal (UBM) layer, and a solder bump, where the UBM layer's thickness is 50% of the solder bump's thickness, and the solder bump covers both outer side surfaces of the UBM layer, dispersing stress and increasing the area of crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a wafer-level package is mounted on a main board, then the package size is minimized, but stress concentrates on the solder bump due to thermal expansion differences
Solution Approach 1:
The UBM layer extends laterally beyond the solder bump footprint in the horizontal dimension, creating an enlarged stress distribution area. This lateral extension allows stress to be dispersed across a larger area rather than being concentrated vertically at the solder bump interface, effectively resolving the stress concentration problem while maintaining the compact package size.
Solution Approach 2:
The UBM layer acts as an intermediary structure between the solder bump and the substrate. It serves as a transition zone that mediates the thermal expansion stress by providing a larger area for stress distribution, protecting the solder bump from direct stress concentration while enabling the compact wafer-level package design.
2Stress or pressure
If the UBM layer thickness is increased to disperse stress, then stress distribution improves, but the manufacturing complexity increases
Solution Approach 1:
The patent optimizes the UBM layer thickness to a specific parameter range (50-150 micrometers) to achieve effective stress distribution. By establishing a quantitative parameter specification, the design balances stress dispersion performance with manufacturing feasibility, avoiding excessive complexity while ensuring adequate stress management.
3Stress or pressure
If the UBM layer thickness is set to 50% of solder bump thickness, then stress is effectively dispersed, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes a quantitative relationship (UBM thickness = 50% of solder bump thickness) to define optimal stress dispersion. This parameter specification provides clear manufacturing targets and tolerances, enabling consistent production while achieving effective stress management through controlled dimensional relationships.
Data Source
AI summary
A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.