Under-Bump Metallization Layout for Dielectric Crack Reduction
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in reducing stress and cracking in dielectric layers due to misalignment of under-bump metallization (UBM) centerlines with via portions, leading to device defects and reduced performance.
Innovation Solution
The implementation of offset or misaligned centerlines for UBMs relative to via portions in the metallization pattern reduces stress in dielectric layers, thereby minimizing cracking and defects by using offset or misaligned centerlines in the UBM layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If UBM centerlines are aligned with via portions, then manufacturing precision is improved, but stress and cracking in dielectric layers increase
Solution Approach 1:
The patent intentionally introduces asymmetry by offsetting the UBM centerlines from the via portion centerlines. This deliberate misalignment creates an asymmetric stress distribution that prevents stress concentration at any single point, thereby reducing overall stress and cracking in the dielectric layers while maintaining acceptable manufacturing precision through controlled offset distances.
Solution Approach 2:
The patent changes the positional parameter of the UBM relative to the via portions by introducing a controlled offset distance. This parameter change transforms the alignment relationship from coincident (zero offset) to displaced (non-zero offset), which reduces stress concentration in the dielectric layers while maintaining制造 feasibility within a viable process window.
2Object-affected harmful factors
If UBM centerlines are offset from via portions, then stress and cracking are reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent optimizes the offset distance parameter to balance stress reduction with manufacturing precision. By carefully controlling the offset distance within specific ranges, the patent achieves sufficient stress mitigation while maintaining alignment precision that falls within the viable process window of manufacturing capabilities.
Solution Approach 2:
The patent applies partial misalignment rather than complete misalignment. The offset distance is controlled to be sufficient to reduce stress and cracking but not so large as to completely compromise alignment precision, representing a balanced partial action that achieves both goals.
3Reliability
If strict alignment is maintained, then device defects are reduced, but stress in dielectric layers increases
Solution Approach 1:
The patent introduces controlled asymmetry in the UBM-via alignment to redistribute stress uniformly across the dielectric layers. This asymmetric positioning prevents stress concentration that would lead to defects, thereby maintaining or even improving device reliability while reducing overall stress levels.
Solution Approach 2:
The patent converts the potentially harmful effect of misalignment into a beneficial stress-reduction mechanism. By deliberately offsetting the UBM from the via portions, the patent transforms what would normally be considered a manufacturing defect into a design feature that reduces stress and prevents cracking, thereby improving device reliability.
Data Source
AI summary
Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.