Redistribution Layer UBM Layout for Lower Stress IC Packaging
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Solution Overview
Problem
Existing integrated circuit packaging technologies face challenges in achieving reliable electrical performance and structural integrity due to stress transmission along interfaces between redistribution layers, leading to poor reliability.
Innovation Solution
The proposed solution involves a packaged integrated circuit with a redistribution layer featuring conductive lines, vias, and pads, where the upper Under-Bump Metallization (UBM) layer has a width less than or equal to the lower UBM layer, reducing stress transmission and enhancing structural reliability by aligning the UBM layers and conductive vias to distribute stress effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the upper UBM layer has a width greater than the lower UBM layer, then the electrical connection area is increased, but stress concentration occurs at the interface between redistribution layers leading to poor reliability
Solution Approach 1:
The patent applies local quality by creating a tapered UBM layer structure where the width varies locally - the upper UBM layer has a width equal to or less than the lower UBM layer, creating a localized geometric variation that specifically addresses stress concentration at the interface while maintaining adequate electrical connection area. This local structural modification prevents stress transmission without compromising overall electrical performance.
2Stress or pressure
If the UBM layer width is reduced, then stress transmission is minimized, but the electrical connection area may be insufficient
Solution Approach 1:
The patent applies parameter changes by carefully controlling the width parameter of the upper UBM layer to be equal to or less than the lower UBM layer width. This parameter optimization creates a balance point where stress transmission is minimized while maintaining sufficient electrical connection area, resolving the contradiction between stress reduction and electrical performance.
3Reliability
If the interface between redistribution layers is not aligned, then manufacturing flexibility is improved, but stress transmission along the interface increases leading to reliability issues
Solution Approach 1:
The patent applies preliminary action by pre-aligning the upper and lower UBM layers and conductive vias before final assembly. This preliminary alignment ensures that stress is distributed evenly along the interface between redistribution layers, preventing stress concentration and improving interface reliability before the package is completed.
Data Source
AI summary
A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.