Semiconductor UBM Pad Via Placement for Stress Management
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Solution Overview
Problem
The complexity of manufacturing semiconductor structures with increased interconnect density leads to unbalanced stress distribution, causing issues like cracking and delamination, particularly when conductive via structures are positioned under under bump metallurgy (UBM) pads, which limits the compact design of semiconductor packages.
Innovation Solution
A semiconductor structure design that defines a keep-out zone for conductive vias within the UBM pad range, allowing the conductive via to be positioned in a specified area covered by the UBM pad, reducing stress and preventing delamination, while maintaining structural strength and enabling a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive via structures are positioned under UBM pads to increase interconnect density, then manufacturing complexity increases, but stress distribution becomes unbalanced causing cracking and delamination
Solution Approach 1:
The UBM pad region is segmented into three distinct zones: a first region where conductive vias are permitted, a second region (keep-out zone) where conductive vias are prohibited, and a third region. This segmentation allows selective placement of conductive vias to achieve interconnect density while preventing stress concentration in critical areas, thereby resolving the contradiction between increased interconnect density and maintained stress distribution uniformity.
2Quantity of substance
If conductive via structures are positioned under UBM pads, then interconnect density increases, but manufacturing complexity and yield loss increase
Solution Approach 1:
The patent establishes keep-out zones and permissive zones for conductive via placement during the design stage, before manufacturing begins. This preliminary definition of allowable via locations provides clear manufacturing guidelines, reducing process complexity and variability while enabling higher interconnect density through optimized via positioning in permitted regions.
3Quantity of substance
If conductive via structures are positioned under UBM pads, then interconnect density increases, but delamination and structural damage occur
Solution Approach 1:
Different regions of the UBM pad are assigned different functional qualities: the first region allows conductive via placement with acceptable stress characteristics, while the second region (keep-out zone) is designated as a protected area with high structural integrity requirements. This local differentiation enables increased interconnect density in appropriate areas while preserving structural strength in critical regions.
Data Source
AI summary
A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.