Semiconductor Package UBM Pattern Warpage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing efficient and cost-effective semiconductor packages with high integration density and reliable conductive terminals, particularly in forming conductive patterns and redistribution structures that require complex processes and materials, leading to issues like warpage and manufacturing defects.
Innovation Solution
A method for manufacturing semiconductor packages involves forming a conductive pattern over a temporary carrier with a de-bonding layer, followed by a redistribution structure and through insulating vias, with a UBM pattern first process that enhances warpage control and routability, and forming conductive terminals using a multi-step printing and reflow process to achieve reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex processes and materials are used to form conductive patterns and redistribution structures, then manufacturing precision and reliability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The conductive pattern formation process is segmented into distinct stages: forming conductive material in openings, planarizing to create a flat surface, and then forming the UBM pattern. This segmentation allows each step to be optimized independently, improving reliability while managing process complexity through systematic breakdown of the manufacturing sequence.
Solution Approach 2:
The UBM pattern is formed in advance before subsequent conductive terminal formation steps. This preliminary action ensures proper adhesion and electrical connectivity are established early in the process, improving final reliability while the standardized sequence helps manage overall process complexity.
2Ease of manufacture
If conventional conductive terminal formation processes are used, then manufacturing simplicity is maintained, but warpage and manufacturing defects increase
Solution Approach 1:
The process applies localized planarization treatment specifically to the conductive pattern areas where conductive terminals will be formed. This local quality improvement addresses warpage and defect issues precisely where they affect terminal formation, rather than requiring global process changes, thus maintaining manufacturing simplicity while improving precision.
Solution Approach 2:
The manufacturing process incorporates parameter changes through controlled planarization and standardized formation sequences that adjust local physical conditions. These parameter adjustments control warpage and reduce defects during conductive terminal formation, improving manufacturing precision without significantly complicating the overall ease of manufacture.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer. A first portion of the UBM pattern physically contacts a via portion of the patterned conductive layer which is tapered toward the UBM pattern, and a second portion of the UBM pattern is connected to the first portion and protruded from the patterned dielectric layer.