Semiconductor Package UBM Routing for Power Loss Reduction
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Solution Overview
Problem
Conventional power switches in integrated circuits face challenges with high resistance and power loss, limiting their ability to handle increased current and leading to a higher likelihood of failure, while also increasing processing complexity.
Innovation Solution
A semiconductor package design featuring a semiconductor substrate with source and drain regions, an intermediate routing structure, a dielectric layer, and an under-bump-metallization (UBM) stack that includes a conductive base layer, a seed layer, and a thick copper layer, allowing for lower resistance and reduced power loss by enabling lateral current propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wire bond packaging is used with multiple conductive routing layers, then electrical coupling between transistors and conductive pads is achieved, but resistance is high and power loss increases
Solution Approach 1:
The patent transitions from planar routing layers to a three-dimensional UBM stack structure. The UBM stack includes multiple conductive layers (base layer, intermediate layer, top layer) stacked vertically, allowing current to propagate laterally through the thick top layer and reducing resistance without requiring complex lateral routing paths.
Solution Approach 2:
The UBM stack employs composite material structure with different conductive layers (copper, aluminum, or other conductive materials) stacked together. Each layer serves specific functions: the base layer provides mechanical support and adhesion, the intermediate layer provides electrical connection, and the thick top layer provides low-resistance current path. This composite structure reduces overall resistance and power loss.
2Reliability
If conventional routing structures are used, then electrical interconnects are provided, but resistance is high leading to higher likelihood of failure
Solution Approach 1:
The patent introduces a vertical dimension with the UBM stack, where the thick top layer (greater than 6 μm, e.g., 9-14 μm) provides a large cross-sectional area for current flow. This three-dimensional current path reduces resistance and improves reliability compared to conventional planar routing.
Solution Approach 2:
The patent changes the thickness parameter of the conductive top layer to be greater than 6 μm (e.g., 9-14 μm), which significantly reduces electrical resistance. This parameter change directly addresses the high resistance problem and reduces power loss, thereby improving reliability.
3Loss of energy
If thicker conductive layers are used to reduce resistance, then power loss is reduced, but processing complexity increases
Solution Approach 1:
The UBM stack structure serves multiple functions: the base layer provides adhesion and mechanical support, the intermediate layer provides electrical connection to the outermost routing layer, and the thick top layer provides low-resistance current path. This multi-functional design reduces the need for additional processing steps that would otherwise be required to achieve similar results.
Solution Approach 2:
The UBM stack is formed as a pre-integrated structure before final bump formation. The multiple conductive layers are deposited and patterned in advance, creating a ready-made low-resistance path that simplifies subsequent processing steps and reduces overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for the construction of power switches with lower resistance and reduced power loss, enabling them to handle increased current with a lower likelihood of failure without significant increases in processing complexity.
Implementation Method 1
a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening
Implementation Method 2
The thick conductive layer may have a thickness greater than 6 μm, e.g., a thickness greater than 9 μm, e.g., a thickness of about 9 to 14 μm. A thickness of the thick conductive layer may be sufficiently large so as to allow electrical current to propagate laterally along the surface of the thick conductive layer and through the electrical interconnects with lower resistance
Data Source
AI summary
A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.