UBM Metallization Side Barrier for Indium Diffusion Blocking
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Solution Overview
Problem
Current electronic chip assembly methods using UBM metallizations face challenges in preventing indium diffusion and contact between solder material and lower gold layers, leading to potential degradation of the chip, especially due to the complexity and cost of double photolithography processes required to align barrier layers effectively.
Innovation Solution
Incorporating an electrically insulating barrier layer made of zinc sulfide or silicon dioxide on the sides of the metal pad, which is formed during the chip manufacturing process using a single photolithography step, preventing contact between the solder material and the lower gold layer and enhancing the mechanical integrity of the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an electrically insulating barrier layer is added to prevent indium diffusion and solder material contact with lower gold layers, then reliability is improved, but device complexity increases
Solution Approach 1:
An electrically insulating barrier layer made of zinc sulfide or silicon dioxide is introduced as an intermediary between the solder material and the lower gold layers. This insulating layer prevents direct contact and indium diffusion to the gold layers while maintaining the electrical functionality of the UBM structure through the conductive barrier layer.
Solution Approach 2:
The UBM structure is enhanced by combining multiple materials with different properties: conductive barrier layers (such as copper or nickel) for electrical functionality and diffusion prevention, and electrically insulating barrier layers (zinc sulfide or silicon dioxide) for additional protection against indium diffusion and solder material contact. This composite approach creates a multi-functional barrier system.
2Manufacturing precision
If double photolithography process is used to align barrier layers effectively, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The formation of both the conductive barrier layer and the electrically insulating barrier layer is merged into a single photolithography process step. The photolithography pattern defines both layers simultaneously, eliminating the need for separate alignment steps and reducing process complexity while maintaining manufacturing precision.
Solution Approach 2:
The insulating barrier layer is formed with preliminary positioning during the same photolithography step that defines the conductive barrier layer. This preliminary action ensures proper alignment and positioning of both barrier layers before subsequent manufacturing steps, avoiding the need for complex post-alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insulating barrier layer effectively prevents indium diffusion and gold-indium alloy formation, reducing the risk of chip degradation while simplifying the manufacturing process by eliminating the need for double photolithography and improving alignment precision.
Implementation Method 1
an electrically insulating barrier layer arranged on and in contact with the side of the first metal layer over the entire periphery of the metal pad
Data Source
Figure 1~3
Figure 4~5B
Figure 6A~6B
AI summary
The present description relates to an electronic chip (11) comprising a substrate (15) and, on one side of the substrate, a metal pad (13) intended to receive a solder material (14), the pad comprising, in order from said face of the substrate, a first metal layer (21), an electrically conductive barrier layer (23) and a second metal layer (25), in which an electrically insulating barrier layer (27) is disposed on and in contact with the flank of the first metal layer (21) over the entire periphery of the metal pad (13).