Package UBM with Sloped Sidewalls and Adhesion Layer
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable packaging of integrated circuit dies due to issues such as delamination and non-uniformity of dielectric layers, particularly in fan-out or fan-in wafer-level packages, which affect the integration density and reliability of electronic components.
Innovation Solution
The process involves forming a package structure with a redistribution structure that includes a first dielectric layer, metallization patterns, and under ball metallizations (UBMs) with sloped sidewalls, along with an adhesion layer and additional dielectric layers to enhance adhesion and reduce delamination, and using a carrier substrate with a release layer for easy detachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used for integrated circuit dies, then the packaging process is simple, but delamination and non-uniformity of dielectric layers occur, reducing reliability
Solution Approach 1:
The package structure is divided into multiple functional layers including first and second dielectric layers, metal layers, and adhesion layers. Each layer serves a specific purpose in preventing delamination and ensuring uniformity, thereby improving reliability through structured segmentation of the packaging system.
Solution Approach 2:
The patent employs composite material structures combining dielectric layers, metal layers, and adhesion layers with different material properties. This composite approach ensures both mechanical strength and electrical functionality while preventing delamination between layers, directly addressing the reliability issue.
2Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but packaging reliability deteriorates due to delamination and non-uniformity
Solution Approach 1:
The patent addresses integration density challenges by extending the solution into the vertical dimension with multiple stacked dielectric and metal layers. This multi-layer architecture allows higher integration density in the planar direction while maintaining reliability through the vertical stacking of functionally specialized layers that prevent delamination.
Solution Approach 2:
Different regions of the package structure are assigned different material properties and functions. Adhesion layers are strategically placed at critical interfaces, while dielectric and metal layers are configured with specific local characteristics to prevent delamination in high-stress areas, thereby maintaining reliability as integration density increases.
3Area of stationary object
If dielectric layers are made thinner to reduce package area, then package size is reduced, but adhesion and uniformity become problematic
Solution Approach 1:
The patent uses composite material structures with multiple dielectric layers of different compositions and properties. This allows thin overall package area while maintaining uniformity and adhesion through the strategic combination of materials that can be deposited with precise thickness control at each layer interface.
Solution Approach 2:
The dielectric structure is segmented into multiple thin dielectric layers separated by metal and adhesion layers. This segmentation allows each thin layer to be manufactured with better uniformity control while the overall package area remains reduced, as each layer can be optimized independently for its specific function.
Data Source
AI summary
Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.