Semiconductor Package UBMs Aligned With Open Vias
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Solution Overview
Problem
Conventional semiconductor packages face reliability issues due to mechanical stress on solder bumps and inadequate contact between bond pads and conductive coatings, as well as voids in apertures that affect electrical connections.
Innovation Solution
A semiconductor package method involving under bump metallizations (UBMs) aligned with open vias in a substrate, where a conductor fills the vias to form external package connections, reducing stress and eliminating the need for underfilling by embedding conductive protrusions within the vias, which are plated with conductive materials like gold and connected through thermo-compression or adhesive bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used to mount the chip onto the substrate, then electrical connections are formed, but mechanical stress results from differential thermal expansions during thermal cycling
Solution Approach 1:
The patent introduces an intermediary structure (open vias with conductive material) between the chip and substrate that serves as a stress-absorbing interface. The vias act as a compliant layer that can accommodate differential thermal expansion between the chip and substrate, reducing mechanical stress on the solder bumps while maintaining electrical connectivity.
Solution Approach 2:
The patent changes the physical parameters of the connection structure by replacing rigid solder bumps with a more compliant conductive material filling open vias. This parameter change allows the connection structure to better accommodate thermal expansion differences, reducing mechanical stress while maintaining electrical connection reliability.
2Reliability
If conductive coatings are applied to bond pads and apertures, then electrical connections are established, but inadequate contact between bond pad, conductive coating and solder material results in reliability issues
Solution Approach 1:
The patent extracts the conductive material from the traditional solder bump form and places it directly within the open vias, eliminating the need for precise alignment and contact between multiple conductive layers. This extraction simplifies the manufacturing process and ensures adequate contact by design rather than by precise assembly.
Solution Approach 2:
The patent merges the bond pad, conductive coating, and solder material functions into a single integrated structure where the conductive material fills the open vias that are aligned with the bond pads. This merging eliminates interface contact issues by creating a continuous conductive path from the bond pad through the via to the external connection.
3Strength
If apertures are filled with adhesive bumps, then mechanical support is provided, but voids formed within the apertures affect electrical connections
Solution Approach 1:
The patent changes the parameter of the via structure from closed apertures to open vias that extend through the substrate to the bottom surface. This parameter change allows the conductive material to form a continuous path without voids, maintaining both mechanical support and electrical connection reliability.
4Reliability
If underfill resin is used to encapsulate solder bumps, then protection is provided, but material costs increase and the process becomes more complex
Solution Approach 1:
The patent extracts the underfill function from the packaging process by designing the open via structure to inherently provide both mechanical support and electrical connection. This elimination of the underfill step simplifies the manufacturing process and reduces material costs while maintaining protection and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of electrical connections by directly linking UBMs or conductive protrusions with external package connections, reducing mechanical stress and eliminating the need for underfilling, thereby improving material efficiency and connection reliability.
Implementation Method 1
Solder material is provided at the opening of the apertures to result in the solder material filling the coated apertures by capillary action and forming solder bumps
Implementation Method 2
The semiconductor device is bonded to the substrate through an adhesive
Data Source
AI summary
A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.