Low-Latency UCIe Interface Module for Chiplet Clock Transmission
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Solution Overview
Problem
The Universal Chiplet Interconnect express (UCIe) standard lacks mechanisms for transmitting transceiver clocks and does not provide flexibility in module alignment, leading to increased latency and inflexibility in inter-chiplet data flow, particularly in high-speed transceiver protocols.
Innovation Solution
A system and method for low-latency data transfer between chiplets using a low-latency synchronous clock forwarded UCIe interface module that bypasses protocol and adapter layers, maintaining transceiver-generated clock characteristics, and includes alignment circuitry for flexible multi-module alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If standard UCIe interface is used for inter-chiplet data transfer, then connectivity is established, but latency increases and transceiver clock characteristics are not preserved
Solution Approach 1:
The interface is segmented into two independent paths: a standard UCIe path for general data transfer and a dedicated low-latency synchronous path for transceiver clock and aligned data transfer. This segmentation allows each path to be optimized for its specific function, preserving clock characteristics while reducing latency.
Solution Approach 2:
A synchronous interface module acts as an intermediary between the transceiver chiplet and the programmable logic chiplet. This intermediary maintains the transceiver-generated clock characteristics and enables low-latency data transfer by bypassing the standard UCIe protocol layers for synchronous data streams.
2Adaptability or versatility
If fixed UCIe module alignment is used, then interface compatibility is maintained, but flexibility in module alignment is reduced
Solution Approach 1:
The interface module incorporates dynamic alignment capabilities that allow it to adapt to different module configurations. The alignment circuitry can be configured to support various module alignments (1:1, 1:2, 2:1, 2:2) depending on the specific application requirements, providing flexibility without requiring complete interface redesign.
3Productivity
If UCIe protocol layers are used for data transfer, then standard compliance is achieved, but data transfer latency increases
Solution Approach 1:
The synchronous data transfer path extracts and bypasses the standard UCIe protocol layers (adapter and protocol layers) for critical data streams. By taking out these intermediate layers, the data transfer path achieves lower latency while maintaining standard compliance through the dedicated synchronous interface module.
Data Source
AI summary
A multi-chiplet system includes a first chiplet comprising a first transceiver and a first chiplet-to-chiplet (C2C) interface module, and a second chiplet comprising programmable logic circuitry and a second C2C interface module. The first transceiver is configured to generate a clock, which is transmitted from the first C2C interface module to the second C2C interface module, through a clock transmission wire, for data transfer between the first chiplet and the second chiplet.