UCIe DDR PHY Signal Mapping for Scalable Memory Dies

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Solution Overview

Problem

Existing memory systems face challenges in efficiently transmitting and receiving DDR PHY interface signals, particularly in high-bandwidth memory applications, leading to increased power consumption and limited scalability in connecting multiple memory devices.

Innovation Solution

The use of a universal chiplet interconnect express (UCIe) interface for die-to-die communication, which converts DDR PHY interface signals to UCIe signals based on specific mappings, reducing power consumption and enhancing scalability by integrating fewer UCIe modules compared to traditional DDR PHY methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If traditional DDR PHY interface methods are used for memory communication, then signal transmission can be achieved, but power consumption increases and scalability is limited

Engineering Contradiction:

Improvepower consumptionVSAvoidscalability

Core Design Contradiction:

Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent changes the interface parameter from traditional DDR PHY interface to UCIe interface, fundamentally altering the signal transmission mechanism. This parameter change enables more efficient data transfer with lower power consumption and improved scalability for connecting multiple memory devices to the CPU.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional mechanical/electrical DDR PHY interface system with a UCIe-based interface system. This substitution involves converting DFI signals to UCIe signals through mapping, achieving superior performance in power efficiency and scalability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If more DFI channels are used to increase bandwidth, then data transmission capacity improves, but device complexity increases

Engineering Contradiction:

Improvedata transmission capacityVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The UCIe interface provides multi-functionality by handling multiple DFI channels through a unified mapping mechanism. The controller-side UCIe circuit and memory-side UCIe circuit can accommodate multiple DFI channels (e.g., three DFI channels mapping to UCIe modules), achieving high data transmission capacity while maintaining manageable device complexity through standardized interface protocols.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250258786A1SYSTEMS AND METHODS FOR TRANSMITTING AND RECEIVING DOUBLE DATA RATE (DDR) PHYSICAL (PHY) INTERFACE (DFI) SIGNALS USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIe)

Publication Date: 2025.08.14 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a method for transmitting and receiving DFI signals using UCIe, the method including receiving, from a memory controller of a first die, a first DFI signal via a first controller-side DFI channel, the first controller-side DFI channel being one of at least two controller-side DFI channels including the first controller-side DFI channel and a second controller-side DFI channel, converting, by a controller-side UCIe circuit of the first die, at least a portion of the first DFI signal to a first UCIe transmit signal based on a mapping between the first controller-side DFI channel, the second controller-side DFI channel, and a first controller-side UCIe module, the first controller-side UCIe module including a UCIe controller and at least a portion of a UCIe physical layer, and transmitting, by the controller-side UCIe circuit, the first UCIe transmit signal to a second die including a memory.