UCIe HBM Interconnect Layout Without EMIB or Interposers

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Solution Overview

Problem

Existing communication interfaces between integrated circuit devices and high bandwidth memory (HBM) devices, such as EMIBs and microbumps, increase complexity and cost while often leading to higher data transfer latency.

Innovation Solution

Implementing a Universal Chiplet Interconnect Express-Memory (UCIe-M) interface that directly couples integrated circuit devices and HBM devices via a package substrate, eliminating the need for interposers and microbumps, and utilizing larger package substrate bumps for signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If EMIB is integrated into the package substrate to enable communication between HBM and integrated circuit device, then data transfer connection is established, but package substrate complexity and cost increase

Engineering Contradiction:
Improvedata transfer connectionVSAvoidpackage substrate complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the EMIB component from the package substrate, eliminating the need for EMIB integration. The HBM device and integrated circuit device are directly mounted to the package substrate using conventional bump techniques, removing the intermediate EMIB structure while maintaining data transfer functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent eliminates the EMIB intermediary component by establishing direct communication paths between HBM and the integrated circuit device through the package substrate itself, using standard routing resources without requiring a separate bridge structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If EMIB is integrated into the package substrate to enable communication between HBM and integrated circuit device, then data transfer connection is established, but data transfer latency increases

Engineering Contradiction:
Improvedata transfer connectionVSAvoiddata transfer latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By removing the EMIB component from the signal path, the patent eliminates the additional signal routing delays associated with EMIB integration, thereby reducing data transfer latency while maintaining connection reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If microbumps are used to mount HBM and integrated circuit device to interposer for communication, then data transfer connection is established, but number of connections is reduced due to small microbump size

Engineering Contradiction:
Improvedata transfer connectionVSAvoidnumber of connections
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent uses conventional, larger-sized bumps instead of precision microbumps, allowing for greater connection density and easier manufacturing while maintaining reliable data transfer connections between HBM and the integrated circuit device.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20260030197A1Chiplet Interconnect for High Bandwidth Memory Devices
Publication Date: 2026.01.29 FOO LOKE YIP
  • US20260030197A1 patent drawing
  • US20260030197A1 patent drawing
  • US20260030197A1 patent drawing

AI summary

Systems or methods of the present disclosure may provide communication interfaces for communicatively coupling integrated circuit devices to high bandwidth memory (HBM) devices. In particular, the communication interfaces may support Universal Chiplet Interconnect Express (UCIe) communications between the integrated circuit devices and the HBM devices. The integrated circuit device and the HBM devices may be directly coupled to a communication bridge, such as a package substrate via package substrate bumps. The package substrate may include routing resources that facilitate communications, such as the transmission and reception of UCIe signals, between the integrated circuit device and the HBM device. As a result, the integrated circuit and the HBM devices may engage in low latency communications without demanding any additional hardware interfaces, such as embedded multi-die interconnect bridges (EMIB) or interposers.