UCIe Memory Die-to-Die Interconnect for Bandwidth and Latency
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Solution Overview
Problem
Existing interconnect architectures in high-performance computing systems face challenges in efficiently managing communication between semiconductor dies, particularly in on-package memory architectures, with limitations in bandwidth, latency, and cost-effectiveness, especially as processing power increases.
Innovation Solution
Implementing a Universal Chiplet Interconnect Express (UCIe) interconnect to facilitate high-bandwidth, low-latency, and cost-effective connectivity between semiconductor dies, including SoC and memory chips within a package, using UCIe interfaces and interface logic to map memory signals to UCIe signals for transport over the interconnect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then electrical communication is achieved, but bandwidth and communication speed are limited
Solution Approach 1:
The patent segments the interconnect architecture from traditional multi-drop buses into dedicated point-to-point serial links. Each link operates independently at high speed, eliminating the bandwidth sharing constraints of bus architectures. This segmentation enables multiple simultaneous communications between processor sockets and other devices, dramatically increasing overall system bandwidth and communication speed.
2Productivity
If processing power increases with more sockets and cores, then computing capability improves, but communication requirements between sockets become more critical and complex
Solution Approach 1:
The patent implements a universal interconnect architecture where the same high-speed serial link infrastructure serves multiple functions: data transfer between sockets, communication with memory, I/O devices, and acceleration engines. This multi-functional approach eliminates the need for separate communication channels for different purposes, reducing interconnect complexity while supporting increased computing power through scalable socket configurations.
3Area of stationary object
If on-package memory architecture is implemented, then integration density increases, but existing interconnect capabilities are insufficient
Solution Approach 1:
The patent introduces high-speed serial links as an intermediary communication medium between the processor socket and on-package memory. These dedicated point-to-point links act as mediators that bridge the computational core and memory subsystem, providing reliable, high-bandwidth communication that overcomes the limitations of traditional on-package memory interconnects. This enables dense integration while maintaining robust communication capabilities.
Data Source
AI summary
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.